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    • 12. 发明申请
    • Dynamically Creating Trick Files To Hide Latency In Streaming Networks
    • 动态创建窍门文件以隐藏流媒体网络中的延迟
    • US20100003008A1
    • 2010-01-07
    • US12165723
    • 2008-07-01
    • Anil ThomasGlenn Connery
    • Anil ThomasGlenn Connery
    • H04N5/91
    • H04N5/783H04N7/17318H04N21/2387H04N21/6125H04N21/6587
    • A system and process are provided to reduce the latency associated with delivery of data for trick functions (e.g., fast-forward or rewind) in data distribution systems. In response to a request for a trick function associated with program data being streamed to a user terminal, first trick data frames for the trick function are retrieved from a first computing apparatus (e.g., a storage server) and in the meantime second trick data frames for the trick function are generated at a second computing apparatus (e.g., streaming server). Until the first trick data frames arrive from the first computing apparatus, the second computing device streams the second trick data frames to the user terminal. The second computing apparatus streams the first trick data frame to the user terminal as they arrive. A user at the user terminal experiences minimal delay in viewing a requested trick function since the second computing apparatus begins sending the trick data to the user terminal before the pre-built trick data arrives for streaming to the user terminal. The streaming server also buffers trick data frames for a current speed trick that may be used for dynamically generating trick data frames a next higher speed trick requested by the user terminal.
    • 提供了一种系统和过程,以减少与数据分发系统中的特技功能(例如,快进或倒带)的数据传送相关联的延迟。 响应于与向流向用户终端的节目数据相关联的特技功能的请求,从第一计算装置(例如,存储服务器)检索特技功能的第一特技数据帧,并且同时从第二特技数据帧 因为在第二计算装置(例如,流服务器)处产生技巧功能。 在第一特技数据帧从第一计算装置到达之前,第二计算装置将第二特技数据帧流向用户终端。 第二计算装置在用户终端到达时将第一特技数据帧流向用户终端。 由于第二计算装置在预先构建的特技数据到达用户终端之前开始向用户终端发送特技数据,因此用户终端中的用户在查看所请求的特技功能时经历最小的延迟。 流服务器还缓存用于当前速度技巧的特技数据帧,其可以用于动态生成用户终端请求的下一个更高速度技巧的特技数据帧。
    • 13. 发明授权
    • Tag echo discovery protocol to detect reachability of clients
    • 标签回波发现协议来检测客户端的可达性
    • US06694369B1
    • 2004-02-17
    • US09539923
    • 2000-03-30
    • RamKrishna VepaJames BinderGlenn Connery
    • RamKrishna VepaJames BinderGlenn Connery
    • G06F1516
    • H04L43/50
    • A method for detecting reachability of client computers communicatively coupled in a computer network to a server computer. A plurality of identifier tags are resident in the memory of the server. The server generates a data packet comprising an I.C.M.P. echo packet and selects a first identifier tag from among the plurality of identifier tags resident in memory, the first identifier tag being chosen to correspond to a first client computer. The server inserts the first identifier tag into the proper data segment of the echo packet and forwards the packet to the first client. After a predetermined time awaiting a responsive ping from the client, the server determines if the client is tag-compliant or non tag-compliant.
    • 一种用于检测在计算机网络中通信耦合到服务器计算机的客户端计算机的可达性的方法。 多个标识符标签驻留在服务器的存储器中。 服务器生成包括I.C.M.P.的数据分组。 回波分组,并且从驻留在存储器中的多个标识符标签中选择第一标识符标签,第一标识符标签被选择为对应于第一客户端计算机。 服务器将第一个标识符标签插入到回发报文的正确数据段,并将报文转发给第一个客户端。 在等待来自客户端的响应ping的预定时间之后,服务器确定客户端是否符合标签或非标签兼容。
    • 14. 发明授权
    • Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory
    • 从处理器到从属存储器数据传输,主处理器将地址写入从属存储器,并向从属处理器和从属存储器提供控制输入
    • US06363444B1
    • 2002-03-26
    • US09464626
    • 1999-12-17
    • John J. PlatkoRobert ReissfelderGlenn Connery
    • John J. PlatkoRobert ReissfelderGlenn Connery
    • G06F1300
    • G06F13/28
    • A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the reading and writing of the memory at addressed locations. A slave processor, such as an optional encryption engine, has a data input/output bus connected to the memory data bus. The master processor also controls the reading and writing of data to/from the slave processor via the memory data bus. The master processor effects data transfers from the memory to the slave processor over the data bus by generating a series of memory addresses to read the data from the memory onto the data bus. As each data word appears on the data bus, it is written into the slave processor. The master processor effects data transfers from the slave processor to the memory over the data bus by reading a series of data from the slave processor onto the data bus, generating a series of memory addresses as the data are being read from the slave processor, and writing each data word into the memory as it appears on the data bus.
    • 诸如嵌入在网络接口卡中的处理器的主处理器经由存储器数据总线耦合到存储器。 主处理器为存储器生成地址,并控制在寻址位置读取和写入存储器。 诸如可选加密引擎的从属处理器具有连接到存储器数据总线的数据输入/输出总线。 主处理器还通过存储器数据总线控制对从处理器的数据的读取和写入。 主处理器通过生成一系列存储器地址从数据总线上的存储器读取数据,从而从数据总线通过数据总线实现从存储器到从属处理器的数据传输。 当数据总线上出现每个数据字时,它将被写入从属处理器。 主处理器通过从从属处理器读取一系列数据到数据总线,通过数据总线实现从从属处理器到存储器的数据传输,当从从处理器读取数据时产生一系列存储器地址,以及 将数据字写入数据总线上显示的内存中。