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11. 发明授权

US06335652B2 Method and apparatus for the replacement of non-operational metal lines in DRAMS 失效
标题翻译：用于替代DRAMS中的非操作金属线的方法和装置
公开(公告)号：US06335652B2
公开(公告)日：2002-01-01
申请号：US09764816
申请日：2001-01-18
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G05F1116
CPC分类号： G11C29/80 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.
摘要翻译：一种半导体集成电路器件，包括用于替换用于连接到电路块的非操作金属线的冗余金属线。本发明还包括一种用于将有缺陷或其它不可操作的导电数据线与其所连接的电路块分离的方法，以及通过将其连接到相同的电路块来用冗余线代替有缺陷的导电数据线。不需要备用导电块。冗余金属线可以在集成电路器件内的多个层级中使用。

12. 发明授权

US06320780B1 Reduced impact from coupling noise in diagonal bitline architectures 有权
标题翻译：减少对角位线结构中耦合噪声的影响
公开(公告)号：US06320780B1
公开(公告)日：2001-11-20
申请号：US09406892
申请日：1999-09-28
申请人： Gerhard Mueller , Ulrike Gruening
发明人： Gerhard Mueller , Ulrike Gruening
IPC分类号： G11C506
CPC分类号： H01L27/10805 , G11C11/4097 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising first and second adjacent signal line pairs 310 and 320 is described. The signal line pairs comprise diagonal signal paths 311p, 312p; 321p and 322p with directional changes 335. The first signal line pair comprises m twists 340, where m is a whole number ≧1, and the second signal line pair comprises n twists 360 and 361, where n is a whole number ≠m.
摘要翻译：描述了包括第一和第二相邻信号线对310和320的集成电路。信号线对包括对角线信号路径311p，312p; 321p和322p具有方向改变335.第一信号线对包括m个扭曲340，其中m是整数> = 1，第二信号线对包括n个捻度360和361，其中n是整数m 。

13. 发明授权

US06292402B1 Prefetch write driver for a random access memory 失效
标题翻译：为随机存取存储器预取写入驱动程序
公开(公告)号：US06292402B1
公开(公告)日：2001-09-18
申请号：US09456589
申请日：1999-12-08
申请人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
发明人： David R. Hanson , Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C1604
CPC分类号： G11C7/1072 , G11C7/1078
摘要： A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.
摘要翻译：用于随机存取存储器（RAM）的预取输入写入驱动器和包括预取输入写入驱动器的RAM。预取输入写入驱动器特别适用于同步动态RAM（SDRAM）。预取输入写入驱动器包括数据输入级接收数据，使能级接收对应的数据使能，以及写入驱动器，响应于写入信号和相应的使能级状态向存储器阵列提供接收到的数据。数据级和使能级可以各自包括两个或多个串联连接的三状态驱动器和每个三状态驱动器的输出端的锁存器。当数据通过数据阶段时，相应的使能状态通过使能阶段。如果使能状态指示要将数据级中的数据写入阵列，则将数据传送到RAM阵列。

14. 发明授权

US06272062B1 Semiconductor memory with programmable bitline multiplexers 有权
标题翻译：具有可编程位线多路复用器的半导体存储器
公开(公告)号：US06272062B1
公开(公告)日：2001-08-07
申请号：US09583596
申请日：2000-05-31
申请人： Gerhard Mueller , Toshiaki Kirihata , Dmitry Netis
发明人： Gerhard Mueller , Toshiaki Kirihata , Dmitry Netis
IPC分类号： G11C800
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C8/12 , G11C11/4097
摘要： There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups; at least one sense amplifier; a first and a second multiplexer; and at least one programmable control device. Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.
摘要翻译：提供一种半导体存储器件，其包括：以至少两组布置的多个存储单元; 至少一个读出放大器; 第一和第二多路复用器; 和至少一个可编程控制装置。每个多路复用器适于将至少一个组耦合到放大器。可编程控制装置适于控制第一和第二多路复用器。在一个实施例中，可编程控制装置适于独立地控制多路复用器。

15. 发明授权

US06259309B1 Method and apparatus for the replacement of non-operational metal lines in DRAMS 失效
标题翻译：用于替代DRAMS中的非操作金属线的方法和装置
公开(公告)号：US06259309B1
公开(公告)日：2001-07-10
申请号：US09305434
申请日：1999-05-05
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G05F1116
CPC分类号： G11C29/80 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit block to which it is connected, and replacing the defective conductive data line with a redundant line by coupling it to the same circuit block. A spare conductive block is not needed. The redundant metal lines may be used in multiple levels of hierarchy within an integrated circuit device.
摘要翻译：一种半导体集成电路器件，包括用于替换用于连接到电路块的非操作金属线的冗余金属线。本发明还包括一种用于将有缺陷或其它不可操作的导电数据线与其所连接的电路块分离的方法，以及通过将其连接到相同的电路块来用冗余线代替有缺陷的导电数据线。不需要备用导电块。冗余金属线可以在集成电路器件内的多个层级中使用。

16. 发明授权

US06215349B1 Capacitive coupled driver circuit 有权
标题翻译：电容耦合驱动电路
公开(公告)号：US06215349B1
公开(公告)日：2001-04-10
申请号：US09265253
申请日：1999-03-09
申请人： David Russell Hanson , Gerhard Mueller
发明人： David Russell Hanson , Gerhard Mueller
IPC分类号： H03K1716
CPC分类号： G11C7/1069 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C11/4096 , H03K19/01707 , H03K19/01728
摘要： A high performance driver circuit is described. The driver produces increased current flow at its output to decrease charging time. Increased current flow is achieved by providing an overdrive circuit that provides a voltage offset to increase the magnitude of the overdrive voltage.
摘要翻译：描述高性能驱动电路。驱动器在其输出端产生增加的电流，以减少充电时间。通过提供提供电压偏移以增加过载驱动电压的幅度的过驱动电路来实现增加的电流。

17. 发明授权

US6110169A Cutting device for electrotomy 有权
标题翻译：电切切割装置
公开(公告)号：US6110169A
公开(公告)日：2000-08-29
申请号：US117874
申请日：1998-08-07
申请人： Gerhard Mueller , Kai Desinger
发明人： Gerhard Mueller , Kai Desinger
IPC分类号： A61B18/14 , A61M1/00 , A61M3/02 , A61B18/18
CPC分类号： A61M3/0279 , A61B18/14 , A61B18/1402 , A61B2018/00178 , A61B2018/126 , A61B2018/1407 , A61B2090/0817
摘要： A cutting device for use in electrotomy is disclosed for use with a high frequency generator to make a cut in a cutting direction. The cutting device comprises a carrier element, and first and second electrodes each connected to the high frequency generator. Each electrode has a proximal portion attached to the carrier element and an elongated distal leg portion which terminates in a distal end. An insulation element connects the distal ends to each other with predetermined spacing between them. The elongated segments oppose each other and are aligned to be co-linear with each other along the cutting direction.
摘要翻译： PCT No.PCT / DE97 / 00232 Sec。 371日期：1998年8月7日 102（e）1998年8月7日PCT PCT 1997年2月3日PCT公布。公开号WO97 / 28751 日期1997年8月14日公开了一种用于电动切割的切割装置，用于与高频发生器一起切割切割方向。切割装置包括载体元件，以及各自连接到高频发生器的第一和第二电极。每个电极具有附接到载体元件的近端部分和终止于远端的细长远端腿部分。绝缘元件将它们之间的预定间隔彼此连接。细长部分彼此相对并且沿着切割方向彼此共线对准。

18. 发明授权

US6086366A Device for removing material from a workpiece by laser radiation 失效
标题翻译：用于通过激光辐射从工件去除材料的装置
公开(公告)号：US6086366A
公开(公告)日：2000-07-11
申请号：US29966
申请日：1998-06-11
申请人： Gerhard Mueller , Thomas Ertl , Hartmut Benthin
发明人： Gerhard Mueller , Thomas Ertl , Hartmut Benthin
IPC分类号： A61C1/00 , A61C13/38 , B23K26/03 , B23K26/06 , B23K26/12
CPC分类号： B23K26/032 , A61C1/0046 , B23K26/0648 , B23K26/0665 , B23K26/12 , B23K26/128
摘要： A device for removing material from a workpiece, in particular for removing a hard substance, such as tooth enamel or dentine from a tooth, or for removing ceramic materials, has a laser for irradiating the workpiece in a locally limited ablation area where material is removed, and a handling part (1) which receives the laser or is connected thereto by an optical fiber element or by a mirror arrangement. The handling part (1) is used to position the laser beam (3) in the ablation area and has a distance measurement device (11 to 15, D1, D2) to monitor the depth of material removal. While the material is being removed, the distance measurement device (11 to 15, D1, D2) measures the distance to the workpiece surface in the ablation area and therefore the depth of material removal by means of the material-removing laser or of a measurement beam (11) generated by another laser.
摘要翻译： PCT No.PCT / DE96 / 01788 Sec。 371日期：1998年6月11日 102（e）1998年6月11日PCT PCT 1996年9月11日PCT公布。公开号WO97 / 12559 日本1997年04月10日用于从工件去除材料的装置，特别是用于从牙齿去除硬质物质如牙釉质或牙质或用于除去陶瓷材料的装置具有用于在局部限制的消融中照射工件的激光移除材料的区域，以及接收激光器或通过光纤元件或通过反射镜布置与其连接的处理部分（1）。处理部分（1）用于将激光束（3）定位在消融区域中，并且具有距离测量装置（11至15，D1，D2）以监测材料去除的深度。当材料被去除时，距离测量装置（11至15，D1，D2）测量在消融区域中与工件表面的距离，因此测量通过材料去除激光或测量的材料去除深度由另一激光产生的光束（11）。

19. 发明授权

US6069815A Semiconductor memory having hierarchical bit line and/or word line architecture 失效
标题翻译：具有分层位线和/或字线架构的半导体存储器
公开(公告)号：US6069815A
公开(公告)日：2000-05-30
申请号：US993538
申请日：1997-12-18
申请人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
发明人： Gerhard Mueller , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C7/18 , G11C8/14 , G11C16/06 , G11C5/06
CPC分类号： G11C7/18 , G11C8/14
摘要： Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.
摘要翻译：公开了具有分级位线和/或字线架构的半导体存储器。在一个实施例中，具有特别适合于小于8F2的小区的分层位线架构的存储器包括每列中的主位线对，包括彼此垂直间隔开的部分的第一和第二主位线。第一和第二主位线在垂直方向上相对于彼此扭曲，使得第一主位线交替地覆盖并位于第二主位线下方。每列中的多个局部位线对耦合到存储器单元，其中至少一个局部位线耦合到主位线。在其他实施例中，公开了分层字线配置，包括主字线，子主字线和本地字线，经由开关，电触点或电路彼此电互连。

20. 发明授权

US5917744A Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines 失效
标题翻译：半导体存储器具有分层位线架构和交错主位线
公开(公告)号：US5917744A
公开(公告)日：1999-06-29
申请号：US993537
申请日：1997-12-18
申请人： Toshiaki Kirihata , Gerhard Mueller
发明人： Toshiaki Kirihata , Gerhard Mueller
IPC分类号： G11C11/401 , G11C7/18 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C11/4097 , G11C7/18
摘要： Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SA.sub.i), at least one pair of master bitlines (MBL.sub.i, MBL.sub.i ) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL.sub.1i, LBL.sub.1i , LBL.sub.2i, LBL.sub.2i ), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch. The master bitlines may be arranged in either folded or open configurations. The master bitline pitch may be about twice the local bitline pitch.
摘要翻译：公开了采用分级位线架构的半导体存储器，其允许加宽的主位线间距以及低位线电容。在示例性实施例中，存储器（30）包括以行和列排列以存储数据的多个存储单元（MC）。每列具有至少一个读出放大器（SAi），可操作地耦合到读出放大器的至少一对主位线（MBLi，+ E，ovs MBLi + EE）和至少两对本地位线（LBL1i，+ E ，ovs LBL1i + EE，LBL2i，+ E，ovs LBL2i + EE），耦合到存储器单元并选择性地耦合到读出放大器。本地位线对中的至少一个经由主位线对选择性地耦合到读出放大器。每个主位线对具有比列长度短的长度，并且主位线被布置成交错配置。至少一些主位线的至少一部分的间距大于局部位线间距。主位线可以以折叠或开放的配置布置。主位线间距可以是本地位线间距的两倍。

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