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11. 发明申请

US20090072361A1 Multi-Chip Stacked Package Structure 审中-公开
标题翻译：多芯片堆叠封装结构
公开(公告)号：US20090072361A1
公开(公告)日：2009-03-19
申请号：US12122779
申请日：2008-05-19
申请人： Geng-Shin SHEN , Yu-Ren Chen
发明人： Geng-Shin SHEN , Yu-Ren Chen
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00015 , H01L2924/00012
摘要： A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads.
摘要翻译：一种多芯片堆叠封装结构，包括：具有顶表面的后表面的引线框架，所述内引线包括多个第一内引线和多个第二内引线并联; 第一芯片固定地连接到引线框架的背面，并且第一芯片具有活性表面和与活性表面的中心区域相邻的多个第一焊盘; 多个第一金属线，电连接第一内引线和第二内引线以及第一芯片的有效表面上的第一焊盘; 固定地连接到引线框架的顶表面的第二芯片，并且第二芯片具有活动表面和与活动表面的中心区域相邻的多个第二焊盘; 设置在引线框架的散热片上的一对间隔件; 多个第二金属线，电连接到第一内引线的顶表面，第二内引线和第二芯片的有效表面上的第二焊盘; 以及封装体，其包封所述第一芯片，所述多个金属线，所述第二芯片，所述多个焊盘，所述第一内引线和所述第二内引线，以及露出所述外引线。

12. 发明授权

US07504714B2 Chip package with asymmetric molding 有权
标题翻译：芯片封装，不对称成型
公开(公告)号：US07504714B2
公开(公告)日：2009-03-17
申请号：US11351651
申请日：2006-02-10
申请人： Geng-Shin Shen
发明人： Geng-Shin Shen
IPC分类号： H01L23/495
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49551 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01079 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.
摘要翻译：提供具有不对称模制的芯片封装，包括引线框架，芯片，粘合剂层，接合线和密封剂。引线框架包括框架体和至少湍流板。框体具有内引线部和外引线部。湍流板向上弯曲以形成凸起部分，并且湍流板的第一端连接到框架体。芯片固定在内引线部分下方，湍流板位于芯片的一侧。粘合剂层设置在芯片和内部引线部分之间，并且接合线分别电连接在芯片和对应的内部引线部分之间。密封剂至少封装芯片，接合线，内引线部分，粘合剂层和湍流板。

13. 发明申请

US20090064494A1 MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE 有权
标题翻译：用于四平面非引线芯片封装结构的制造工艺
公开(公告)号：US20090064494A1
公开(公告)日：2009-03-12
申请号：US12270666
申请日：2008-11-13
申请人： Geng-Shin Shen , Chun-Ying Lin
发明人： Geng-Shin Shen , Chun-Ying Lin
IPC分类号： H05K3/10
CPC分类号： H01L21/4857 , H01L21/561 , H01L23/3128 , H01L23/49558 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/97 , H01L2224/274 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01028 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/181 , Y10T29/4913 , Y10T29/49155 , H01L2924/00014 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer are between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.
摘要翻译：提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。首先，提供图案化导电层和图案化导电层上的图案化阻焊层。多个芯片被结合到图案化的阻焊层上，使得图案化的阻焊层位于芯片和图案化的导电层之间。芯片通过多根接合线与图案化导电层电连接，其中芯片和接合线位于图案化导电层的同一侧。形成至少一种模塑料以封装图案化的导电层，图案化的阻焊层，芯片和接合线。然后，分离模塑料，图案化导电层和图案化阻焊层。

14. 发明申请

US20090026632A1 CHIP-TO-CHIP PACKAGE AND PROCESS THEREOF 审中-公开
标题翻译：芯片到芯片包装及其处理
公开(公告)号：US20090026632A1
公开(公告)日：2009-01-29
申请号：US12244553
申请日：2008-10-02
申请人： Geng-Shin Shen , Chun-Hung Lin
发明人： Geng-Shin Shen , Chun-Hung Lin
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/49575 , H01L21/563 , H01L21/6836 , H01L23/3107 , H01L23/4951 , H01L23/49513 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/0401 , H01L2224/06135 , H01L2224/06136 , H01L2224/16145 , H01L2224/16225 , H01L2224/274 , H01L2224/29007 , H01L2224/29101 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73265 , H01L2224/81192 , H01L2224/81801 , H01L2224/83191 , H01L2224/83194 , H01L2224/83855 , H01L2224/83856 , H01L2224/85 , H01L2224/92147 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A wafer treating method for making adhesive chips is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform an adhesive film having B-stage property which has a glass transition temperature between −40 and 175 degree C., for example. After positioning the wafer, the wafer is singulated to form a plurality of chips with adhesive for chip-to-chip stacking, chip-to-substrate or chip-to-lead frame attaching.
摘要翻译：提供了制造粘合剂芯片的晶片处理方法。具有两级特性的液体粘合剂涂覆在晶片的表面上。然后，将晶片预固化，以使液体粘合剂例如具有玻璃化转变温度在-40至175℃之间的具有B阶特性的粘合剂膜。在晶片定位之后，晶片被单片化以形成具有用于芯片到芯片堆叠，芯片到衬底或芯片到引线框架连接的粘合剂的多个芯片。

15. 发明申请

US20080308915A1 CHIP PACKAGE 审中-公开
标题翻译：芯片包装
公开(公告)号：US20080308915A1
公开(公告)日：2008-12-18
申请号：US12198526
申请日：2008-08-26
申请人： Geng-Shin Shen , David Wei Wang
发明人： Geng-Shin Shen , David Wei Wang
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/3121 , H01L23/3185 , H01L23/49513 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83856 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A chip package including a circuit substrate, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface, a first rear surface and first bonding pads, the first rear surface is adhered on the circuit substrate and the first chip is electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first bonding pads of the first chip. The component is disposed over the first active surface of the first chip. The first adhesive layer adhered between the first active surface and the component without covering the first bonding pads and includes a first B-staged adhesive layer adhered on a portion of the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component.
摘要翻译：提供了包括电路基板，第一芯片，第一接合线，部件，第一粘合层和模塑料的芯片封装。第一芯片具有第一有源面，第一后表面和第一接合焊盘，第一后表面粘附在电路基板上，第一芯片与电路基板电连接。第一接合线与电路基板和第一芯片的第一接合焊盘电连接。该部件设置在第一芯片的第一有源表面上。所述第一粘合剂层粘附在所述第一活性表面和所述组分之间，而不覆盖所述第一接合焊盘，并且包括附着在所述第一芯片的所述第一有源表面的一部分上的第一B阶粘合剂层和粘附到所述第一有源表面的第二B阶粘合剂层在第一B阶粘合剂层和组分之间。

16. 发明申请

US20080308914A1 CHIP PACKAGE 审中-公开
标题翻译：芯片包装
公开(公告)号：US20080308914A1
公开(公告)日：2008-12-18
申请号：US12198517
申请日：2008-08-26
申请人： Geng-Shin Shen , David Wei Wang
发明人： Geng-Shin Shen , David Wei Wang
IPC分类号： H01L23/12
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/3121 , H01L23/3185 , H01L23/49513 , H01L23/49575 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/32265 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2224/83856 , H01L2224/85 , H01L2225/0651 , H01L2225/06558 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19107 , H01L2924/00015 , H01L2924/00 , H01L2224/05599 , H01L2224/48227 , H01L2924/00012
摘要： A chip package including a circuit substrate having an opening, a first chip, first bonding wires, a component, a first adhesive layer and a molding compound is provided. The first chip has a first active surface and a first rear surface opposite to the first active surface, the first chip is flipped on and electrically connected with the circuit substrate. The first bonding wires are electrically connected with the circuit substrate and the first chip, and each first bonding wire passes through the opening. The component is disposed over the first rear surface. The first adhesive layer adhered between the first rear surface and the component includes a first B-staged adhesive layer adhered on the first rear surface and the component and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the component. The molding compound is disposed on the circuit substrate.
摘要翻译：提供了包括具有开口的电路基板，第一芯片，第一接合线，部件，第一粘合层和模塑料的芯片封装。第一芯片具有第一有源表面和与第一有源表面相对的第一后表面，第一芯片被翻转并与电路基板电连接。第一接合线与电路基板和第一芯片电连接，并且每个第一接合线穿过开口。该部件设置在第一后表面上。附着在第一后表面和部件之间的第一粘合剂层包括附着在第一后表面上的第一B阶粘合剂层和部件，以及粘附在第一B阶粘合剂层和部件之间的第二B阶粘合剂层。模塑料配置在电路基板上。

17. 发明申请

US20070085186A1 Stacked-type chip package structure 有权
标题翻译：堆叠式芯片封装结构
公开(公告)号：US20070085186A1
公开(公告)日：2007-04-19
申请号：US11255710
申请日：2005-10-19
申请人： Geng-Shin Shen
发明人： Geng-Shin Shen
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L24/73 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/731 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06575 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Besides, the first bonding pads are electrically connected to the substrate through the bonding wires. The second chip is disposed above the first chip, and it has second bonding pads disposed on an active surface thereof. The second bonding pads of the second chip are electrically connected to the first bonding pads of the first chip through the B-stage conductive bumps respectively, and each B-stage conductive bump covers a portion of the corresponding bonding wire.
摘要翻译：提供了包括基板，第一芯片，接合线，第二芯片和B级导电凸块的堆叠型芯片封装结构。第一芯片设置在基板上，并且其第一接合焊盘设置在其有效表面上。此外，第一接合焊盘通过接合线电连接到基板。第二芯片设置在第一芯片上方，并且其第二焊盘设置在其活性表面上。第二芯片的第二焊盘分别通过B级导电凸块电连接到第一芯片的第一焊盘，并且每个B级导电凸块覆盖相应接合线的一部分。

18. 发明申请

US20070063344A1 Chip package structure and bumping process 审中-公开
公开(公告)号：US20070063344A1
公开(公告)日：2007-03-22
申请号：US11234774
申请日：2005-09-22
申请人： Chun-Hung Lin , Geng-Shin Shen
发明人： Chun-Hung Lin , Geng-Shin Shen
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L25/0657 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/90 , H01L2224/05571 , H01L2224/05573 , H01L2224/13144 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/731 , H01L2224/73265 , H01L2224/83192 , H01L2224/83856 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/0781 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A chip package structure including a first substrate, a second substrate, bumps and adhesive blocks is provided. The first substrate has first bonding pads. The second substrate is disposed above the first substrate and has second bonding pads. The bumps are respectively arranged on the first bonding pads or the second bonding pads, and the second substrate is electrically connected to the first substrate through the bumps. The adhesive material with B-stage property are respectively arranged between the first bonding pads and the second bonding pads and enclose each bump. The bumps can be stud bumps or plating bumps.

19. 发明申请

US20060145314A1 Tape for tape carrier package 审中-公开
标题翻译：胶带载带包装
公开(公告)号：US20060145314A1
公开(公告)日：2006-07-06
申请号：US11202898
申请日：2005-08-12
申请人： Hung-Che Shen , Hung-Hsin Liu , Geng-Shin Shen
发明人： Hung-Che Shen , Hung-Hsin Liu , Geng-Shin Shen
IPC分类号： H01L23/495
CPC分类号： H01L23/49572 , H01L23/13 , H01L24/50 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： The invention provides a tape for a tape carrier package. The tape includes a flexible insulating film. The flexible insulating film is divided into a plurality of units arranged successively, and each of the units has a device hole and a plurality of leads. The plurality of leads are formed on the flexible insulating film and protrude to the device hole. The device hole has a plurality of corners formed in a form of a notch for preventing the stress from concentrating on and breaking the leads.
摘要翻译：本发明提供了一种用于带载包装的带子。胶带包括柔性绝缘膜。柔性绝缘膜被分成依次布置的多个单元，并且每个单元具有装置孔和多个引线。多个引线形成在柔性绝缘膜上并突出到器件孔。设备孔具有形成为凹口形式的多个拐角，用于防止应力集中和断开引线。

20. 发明申请

US20120313234A1 QFN PACKAGE AND MANUFACTURING PROCESS THEREOF 审中-公开
标题翻译： QFN封装及其制造工艺
公开(公告)号：US20120313234A1
公开(公告)日：2012-12-13
申请号：US13158124
申请日：2011-06-10
申请人： Geng-Shin SHEN
发明人： Geng-Shin SHEN
IPC分类号： H01L23/495 , H01L21/56 , H01L21/60
CPC分类号： H01L24/11 , H01L21/56 , H01L21/561 , H01L23/3107 , H01L23/4951 , H01L23/49551 , H01L23/49861 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05569 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/13007 , H01L2224/13022 , H01L2224/13082 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13562 , H01L2224/1357 , H01L2224/13644 , H01L2224/16245 , H01L2224/8191 , H01L2224/94 , H01L2924/00014 , H01L2924/181 , H01L2924/351 , H01L2224/11 , H01L2224/05552 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.
摘要翻译：本发明提供一种四平坦无铅（QFN）封装，其包括芯片，引线框架，多个复合凸块和密封剂。芯片具有多个焊盘，引线框架具有多个引线。多个复合凸块中的每一个具有第一导电层和第二导电层。第一导电层电连接在一个焊盘和第二导电层之间，并且第二导电层电连接在第一导电层和引线之一之间。密封剂封装芯片，引线和复合凸块。由此，在提供芯片接合到引线框架之前，在引线框架的引线的间隙之间形成具有复合凸块和半固化密封剂的QFN封装。

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