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11. 发明授权

US5789801A Varactor with electrostatic barrier 失效
标题翻译：变压器带静电屏障
公开(公告)号：US5789801A
公开(公告)日：1998-08-04
申请号：US555777
申请日：1995-11-09
申请人： Edward B. Stoneham
发明人： Edward B. Stoneham
IPC分类号： H01L29/93
CPC分类号： H01L29/93
摘要： A varactor comprising a substrate of semiconductor material on which is grown both an electrostatic barrier having a first layer of material doped with donor impurities and a second layer of material doped with acceptor impurities and a depletable layer. In other embodiments of the present invention varactors are provided that include a plurality of barrier and depletable layer pairs grown in a serial arrangement.
摘要翻译：一种变容二极管，包括半导体材料的衬底，其上生长具有掺杂有施主杂质的第一材料层的静电势垒和掺杂有受主杂质的第二材料层和可消除层。在本发明的其它实施例中，提供了可变电抗器，其包括以串联方式生长的多个屏障和可消除层对。

12. 发明授权

US10568174B1 Apparatus and methods for controlling LED light flux 有权
公开(公告)号：US10568174B1
公开(公告)日：2020-02-18
申请号：US16337412
申请日：2017-10-02
申请人： Edward B. Stoneham
发明人： Edward B. Stoneham
IPC分类号： H05B33/08
摘要： A rectangular pulse generator system is operatively configured to generate a generator output signal, the generator output signal formed as a base rectangular waveform gated by a modulating rectangular waveform, the base rectangular waveform having a first frequency and the modulating rectangular waveform having a second frequency less than the first frequency. A low-pass filter coupled to the rectangular pulse generator system is configured to receive a filter input signal representative of the generator output signal and to produce a filter output signal representative of the filter input signal. A voltage-controlled current source coupled to the low-pass filter generates a drive signal conducted by at least one LED producing a light flux determined by the current level of the LED drive signal. Methods are devised for calibration and for setting the average light flux level.

13. 发明申请

US20200020382A1 DIGITAL-UNIT INTERFACE 审中-公开
公开(公告)号：US20200020382A1
公开(公告)日：2020-01-16
申请号：US16337777
申请日：2017-10-02
申请人： Edward B. Stoneham
发明人： Edward B. Stoneham
IPC分类号： G11C11/4091 , G11C11/4074 , G11C11/4072 , G11C11/4099
摘要： A digital-unit interface comprises a first node, a second node, a third node, and an amplifier assembly. The first node is connected to a pull-up resistor and is configured to be connected to the signal line of a transmission line connected to a first digital unit at a distal point. The second node is configured to be connected to a second reference electrical potential, a signal-return line of the transmission line, and a signal-return line of a second digital unit. The third node is configured to be connected to a signal line of the second digital unit. The amplifier assembly is configured to be connected between the first node and the third node and to transform between high electrical potentials on the first node and lower electrical potentials on the third node while the second digital unit communicates with the first digital unit.

14. 发明授权

US6023209A Coplanar microwave circuit having suppression of undesired modes 失效
标题翻译：共面微波电路抑制不需要的模式
公开(公告)号：US6023209A
公开(公告)日：2000-02-08
申请号：US675931
申请日：1996-07-05
申请人： Mark V. Faulkner , Edward B. Stoneham , Clifford A. Mohwinkel , Mark J. Vaughan
发明人： Mark V. Faulkner , Edward B. Stoneham , Clifford A. Mohwinkel , Mark J. Vaughan
IPC分类号： H01P1/162 , H01P3/00 , H01P3/08 , H01L29/40 , H01P5/00
CPC分类号： H01L23/66 , H01P1/162 , H01P3/003 , H01L2223/6627 , H01L2924/0002
摘要： Two or three conductor coplanar transmission lines and lossy coplanar resistive films are formed on a surface of a substrate. The resistive film dimensions and resistivity are selected to suppress various spurious electromagnetic modes within and around the substrate. The resistive films may be positioned along the outer edges of the transmission lines or between the transmission line conductors. The resistive film may have regular spaced openings for producing an average resistivity different than that of a continuous resistive film. In one embodiment, a signal conductor has a serpentine shape and resistive film elements are positioned between adjacent sections of the signal conductor. In another embodiment, interdigitated resistive film elements extend between transmission line conductors.
摘要翻译：在基板的表面上形成两个或三个导体共面传输线和有损共面的电阻膜。选择电阻膜尺寸和电阻率来抑制衬底内和周围的各种杂散电磁模式。电阻膜可以沿着传输线的外边缘或传输线导体之间的位置。电阻膜可以具有规则间隔的开口，用于产生不同于连续电阻膜的平均电阻率的平均电阻率。在一个实施例中，信号导体具有蛇形形状，并且电阻膜元件位于信号导体的相邻部分之间。在另一个实施例中，交错电阻膜元件在传输线导体之间延伸。

15. 发明授权

US4788156A Subchannel doping to reduce short-gate effects in field effect transistors 失效
标题翻译：子信道掺杂以减少场效应晶体管中的短栅效应
公开(公告)号：US4788156A
公开(公告)日：1988-11-29
申请号：US911270
申请日：1986-09-24
申请人： Edward B. Stoneham , Masahiro Omori , Arthur D. Herbig
发明人： Edward B. Stoneham , Masahiro Omori , Arthur D. Herbig
IPC分类号： H01L29/10 , H01L21/265 , H01L21/324
CPC分类号： H01L29/1075
摘要： One embodiment of a process in accordance with our invention includes the step of forming a P type region on a semiconductor substrate. After the P type region is formed, an N type layer is epitaxially grown on the P type region. A Schottky gate is then formed on the N type epitaxial layer. A first portion of the epitaxial layer serves as a transistor source, a second portion of the epitaxial layer serves as the transistor drain, and a third portion of the epitaxial layer serves as the channel. Of importance, the P type semiconductor region helps prevent various short channel effects caused when current carriers flowing between the source and drain flow too far from the Schottky gate.
摘要翻译：根据本发明的方法的一个实施方案包括在半导体衬底上形成P型区域的步骤。在形成P型区之后，在P型区上外延生长N型层。然后在N型外延层上形成肖特基栅极。外延层的第一部分用作晶体管源极，外延层的第二部分用作晶体管漏极，外延层的第三部分用作沟道。重要的是，P型半导体区域有助于防止在源极和漏极之间流动的载流子流过与肖特基栅极太远时引起的各种短沟道效应。

16. 发明授权

US07710219B2 Merged-filter multiplexer 有权
标题翻译：合并滤波多路复用器
公开(公告)号：US07710219B2
公开(公告)日：2010-05-04
申请号：US12039536
申请日：2008-02-28
申请人： Edward B. Stoneham
发明人： Edward B. Stoneham
IPC分类号： H01P5/12 , H03H7/46
CPC分类号： H01P1/213 , H01P1/2135 , H03D7/02
摘要： A multiplexer circuit may include a first-frequency-quarter-wavelength transmission line extending between a junction between a common terminal and a second-frequency terminal, and a first-frequency low-impedance circuit electrically directly connecting the first transmission line to a circuit ground. In some examples, a second-frequency-quarter-wavelength transmission line may extend between the first transmission line and a third-frequency terminal. A second-frequency low-impedance circuit may electrically directly connect the second transmission line to the circuit ground. The first and second transmission lines and the first and second low-impedance circuits may provide a third-frequency transmission line. A further second-frequency low-impedance circuit may electrically couple the second terminal to the first transmission line. A third-frequency low-impedance circuit may electrically couple the second terminal to the circuit ground. The first-frequency, further second-frequency, and third-frequency low-impedance circuits and the first transmission line may provide in combination a second-frequency transmission line.
摘要翻译：多路复用器电路可以包括在公共端子和第二频率端子之间的连接点之间延伸的第一频率四分之一波长的传输线，以及将第一传输线电连接到电路接地的第一频率低阻抗电路。在一些示例中，第二频率四分之一波长的传输线可以在第一传输线和第三频率终端之间延伸。第二频率低阻抗电路可以将第二传输线电连接到电路接地。第一和第二传输线以及第一和第二低阻抗电路可以提供第三频率传输线。另一个第二频率低阻抗电路可以将第二端子电耦合到第一传输线。第三频率低阻抗电路可以将第二端子电耦合到电路接地。第一频率，第二频率和第三频率低阻抗电路和第一传输线可以组合提供第二频率传输线。

17. 发明授权

US07588966B2 Chip mounting with flowable layer 有权
标题翻译：带可流动层的芯片安装
公开(公告)号：US07588966B2
公开(公告)日：2009-09-15
申请号：US12042144
申请日：2008-03-04
申请人： Edward B. Stoneham , Thomas M. Gaudette
发明人： Edward B. Stoneham , Thomas M. Gaudette
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L24/32 , H01L23/13 , H01L24/48 , H01L24/83 , H01L25/0655 , H01L2224/05554 , H01L2224/27013 , H01L2224/45014 , H01L2224/48091 , H01L2224/48137 , H01L2224/73265 , H01L2224/83051 , H01L2224/8385 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1423 , H01L2924/1433 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/45015 , H01L2924/207
摘要： A circuit structure may be formed in a substrate having a face and an open trench, where one or more chips are to be mounted. At least one bridge may extend across an intermediate portion of the trench, and optionally, may divide the trench into sections. A conductive adhesive layer may be applied to the substrate face and, if included, the bridge. One or more circuit chips may be mounted on the adhesive layer, with at least one edge of one circuit chip adjacent to the trench. Alternatively or additionally, an adhesive layer may be applied to a base of a chip and then mounted to the substrate face, in like fashion. The trench may accommodate excess adhesive flowing out from under the one or more chips, while the bridge retains the adhesive across the width of the trench. If the adhesive is conductive, this provides continuity of the conductive layer on the face of the substrate across the trench. In one example, pairs of circuit chips may be effectively mounted in adjacent relationship for interconnection without interference from excess adhesive.
摘要翻译：电路结构可以形成在具有面和开放沟槽的衬底中，其中将安装一个或多个芯片。至少一个桥可以延伸穿过沟槽的中间部分，并且可选地，可以将沟槽划分成多个部分。可以将导电粘合剂层施加到基板表面，如果包括桥，则应用导电粘合剂层。一个或多个电路芯片可以安装在粘合剂层上，其中一个电路芯片的至少一个边缘与沟槽相邻。或者或另外，粘合剂层可以施加到芯片的基部，然后以类似的方式安装到基板面。沟槽可以容纳从一个或多个芯片下面流出的多余的粘合剂，同时桥将粘合剂保持在沟槽的宽度上。如果粘合剂是导电的，则这提供了穿过沟槽的衬底的表面上的导电层的连续性。在一个示例中，电路芯片对可以有效地安装在相邻的关系中用于互连，而不会受到多余粘合剂的干扰。

18. 发明申请

US20080153206A1 CHIP MOUNTING WITH FLOWABLE LAYER 有权
标题翻译：芯片安装与流动层
公开(公告)号：US20080153206A1
公开(公告)日：2008-06-26
申请号：US12042144
申请日：2008-03-04
申请人： Edward B. STONEHAM , Thomas M. GAUDETTE
发明人： Edward B. STONEHAM , Thomas M. GAUDETTE
IPC分类号： H01L21/00
CPC分类号： H01L24/32 , H01L23/13 , H01L24/48 , H01L24/83 , H01L25/0655 , H01L2224/05554 , H01L2224/27013 , H01L2224/45014 , H01L2224/48091 , H01L2224/48137 , H01L2224/73265 , H01L2224/83051 , H01L2224/8385 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1423 , H01L2924/1433 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/45015 , H01L2924/207
摘要： A circuit structure may be formed in a substrate having a face and an open trench, where one or more chips are to be mounted. At least one bridge may extend across an intermediate portion of the trench, and optionally, may divide the trench into sections. A conductive adhesive layer may be applied to the substrate face and, if included, the bridge. One or more circuit chips may be mounted on the adhesive layer, with at least one edge of one circuit chip adjacent to the trench. Alternatively or additionally, an adhesive layer may be applied to a base of a chip and then mounted to the substrate face, in like fashion. The trench may accommodate excess adhesive flowing out from under the one or more chips, while the bridge retains the adhesive across the width of the trench. If the adhesive is conductive, this provides continuity of the conductive layer on the face of the substrate across the trench. In one example, pairs of circuit chips may be effectively mounted in adjacent relationship for interconnection without interference from excess adhesive.
摘要翻译：电路结构可以形成在具有面和开放沟槽的衬底中，其中将安装一个或多个芯片。至少一个桥可以延伸穿过沟槽的中间部分，并且可选地，可以将沟槽划分成多个部分。可以将导电粘合剂层施加到基板表面，如果包括桥，则应用导电粘合剂层。一个或多个电路芯片可以安装在粘合剂层上，其中一个电路芯片的至少一个边缘与沟槽相邻。或者或另外，粘合剂层可以施加到芯片的基部，然后以类似的方式安装到基板面。沟槽可以容纳从一个或多个芯片下面流出的多余的粘合剂，同时桥将粘合剂保持在沟槽的宽度上。如果粘合剂是导电的，则这提供了穿过沟槽的衬底的表面上的导电层的连续性。在一个示例中，电路芯片对可以有效地安装在相邻的关系中用于互连，而不会受到多余粘合剂的干扰。

19. 发明授权

US07119633B2 Compensated interdigitated coupler 有权
公开(公告)号：US07119633B2
公开(公告)日：2006-10-10
申请号：US10925684
申请日：2004-08-24
申请人： Edward B. Stoneham
发明人： Edward B. Stoneham
IPC分类号： H01P5/18
CPC分类号： H01P1/183
摘要： A coupler may include four ports, and first and second sets of conductive strips. Each set of conductive strips may include a plurality of interconnected conductive strips connected between two ports. Each conductive strip of the first set may be electromagnetically coupled to a conductive strip of the second set. Conductive tabs capacitively coupled directly or indirectly to the ground conductor may extend from conductive strips of the first and second sets. An interconnection may be positioned between adjacent tabs, the interconnection connecting conductive strips of one of the sets of conductive strips. The adjacent tabs may be spaced different distances from the interconnection.

20. 发明授权

US5821827A Coplanar oscillator circuit structures 失效
标题翻译：共面振荡器电路结构
公开(公告)号：US5821827A
公开(公告)日：1998-10-13
申请号：US769144
申请日：1996-12-18
申请人： Clifford A. Mohwinkel , Edward B. Stoneham
发明人： Clifford A. Mohwinkel , Edward B. Stoneham
IPC分类号： H03B5/18 , H01P7/08
CPC分类号： H03B5/1852
摘要： An oscillator circuit having a flip chip metalization pattern and base substrate metalization pattern is defined such that a common-drain oscillator is configured with the common drain interposed between the source and gate terminals, providing an effective RF common reference with reduced parasitic inductance elements which otherwise degrade oscillator power and phase noise at high frequencies. Multiple sets of such patterns on the substrate and such three-terminal devices on the flip chip are arranged such that conductor patterns on the substrate connecting separately from the gates and the sources of the multiple devices to the common-drain reference are easily configured into separable tuning (or resonator) and feedback circuits. A common-drain oscillator having an interdigitated capacitor coplanar cavity resonator circuit as the gate input circuit having reduced distributed inductance is realized utilizing the interposed common-drain connections provided thereby. Having many small devices, such as FETs, coupled closely together (each having very low parasitic and therefore very high potential operating frequency), the signal power of each adds arithmetically but the noise power adds statistically thereby achieving lower phase noise relative to the combined oscillator signal power. Circuit structures utilizing this invention can provide very large oscillator arrays providing a reduction in phase noise relative to the oscillation signal without having the usual device size limitations.
摘要翻译：定义了具有倒装芯片金属化图案和基底金属化图案的振荡器电路，使得公共漏极振荡器配置有插入在源极和栅极端子之间的公共漏极，从而提供有效的RF公共参考，其中减少的寄生电感元件在高频下降低振荡器功率和相位噪声。衬底上的多组这样的图案和倒装芯片上的这样的三端器件被布置成使得与栅极和多个器件的源极分开连接到衬底的衬底上的导体图案容易地配置成可分离调谐（或谐振器）和反馈电路。使用由此提供的插入式共漏极连接，实现了具有分叉电容器共面空腔谐振器电路的共漏极振荡器作为具有降低的分布电感的栅极输入电路。具有诸如FET的许多小器件（每个具有非常低的寄生因素，因此具有非常低的寄生电位，因此具有非常高的潜在工作频率），每个信号功率都是算术的，但是噪声功率统计地增加，从而相对于组合振荡器实现较低的相位噪声信号功率利用本发明的电路结构可以提供非常大的振荡器阵列，其提供相对于振荡信号的相位噪声的降低，而不需要通常的器件尺寸限制。

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