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11. 发明申请

US20150378923A1 Data Bus Efficiency Via Cache Line Usurpation 有权
公开(公告)号：US20150378923A1
公开(公告)日：2015-12-31
申请号：US14835936
申请日：2015-08-26
申请人： Emulex Corporation
发明人： Steven Gerard LeMire , Vuong Cao Nguyen
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0835 , G06F12/0893 , G06F2212/1024 , G06F2212/1044 , G06F2212/604 , G06F2212/6046 , G06F2212/608 , G06F2212/621
摘要： Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.

12. 发明申请

US20150350112A1 HIGH PERFORMANCE ETHERNET NETWORKING UTILIZING EXISTING FIBRE CHANNEL FABRIC HBA TECHNOLOGY 审中-公开
公开(公告)号：US20150350112A1
公开(公告)日：2015-12-03
申请号：US14823282
申请日：2015-08-11
申请人： Emulex Corporation
发明人： Kenneth Hiroshi HIRATA , Stuart Bruce BERMAN
IPC分类号： H04L12/931 , H04L29/12
CPC分类号： H04L49/351 , H04L12/462 , H04L29/12801 , H04L29/12839 , H04L49/357 , H04L61/6004 , H04L61/6022
摘要： This is directed to providing Fibre Channel over Ethernet communication. For example a Fibre Channel over Ethernet (FCoE) enabled device (such as a computer) may include a Fibre Channel over Ethernet Adapter (FCoEA). The FCoEA may include an HBA module. The HBA module may be configured to communicate over the Fibre Channel protocol. The FCoE enabled device may process and encapsulate the HBA module's communication in order to send them over an Ethernet network instead. The FCoE enabled device may process communications directed to various Fibre Channel fabric services by utilizing existing Ethernet services, such as an iSNS server. Thus, the FCoE enabled device can emulate a Fibre Channel network for the HBA module using the Ethernet network and one or more Existing Ethernet services/servers.

13. 发明授权

US09195605B2 Data bus efficiency via cache line usurpation 有权
标题翻译：数据总线效率通过缓存线篡夺
公开(公告)号：US09195605B2
公开(公告)日：2015-11-24
申请号：US14687470
申请日：2015-04-15
申请人： Emulex Corporation
发明人： Steven Gerard LeMire , Vuong Cao Nguyen
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/0835 , G06F12/0893 , G06F2212/1024 , G06F2212/1044 , G06F2212/604 , G06F2212/6046 , G06F2212/608 , G06F2212/621
摘要： Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
摘要翻译：本发明的实施例允许用户更有效地向主存储器分配高速缓冲存储器。处理器或用户分配高速缓冲存储器并将缓存存储器与主存储器位置相关联，但是抑制或绕过将主存储器数据读取到高速缓冲存储器中。本发明的一些实施例允许用户指定在给定时间分配多少高速缓存行。此外，本发明的实施例可以将高速缓存存储器初始化为指定的模式。高速缓冲存储器可以被归零或设置为某些期望的模式，例如所有模式。或者，用户可以通过处理器确定初始化模式。

14. 发明授权

US09183167B2 Enhanced I/O performance in a multi-processor system via interrupt affinity schemes 有权
标题翻译：通过中断关联方案在多处理器系统中提高I / O性能
公开(公告)号：US09183167B2
公开(公告)日：2015-11-10
申请号：US14087953
申请日：2013-11-22
申请人： EMULEX CORPORATION
发明人： Qiang Liu , Allen Russell Andrews , David Bradley Baldwin
IPC分类号： G06F3/00 , G06F13/24
CPC分类号： G06F13/32 , G06F3/061 , G06F3/0632 , G06F3/067 , G06F9/4812 , G06F9/5033 , G06F13/24
摘要： Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.
摘要翻译：这里公开了一种用于改善具有多个CPU的主机系统中的输入/输出（I / O）性能的方法。在这种方法下，提供了各种中断相关性方案，它们将多个处理器，中断和I / O通道相关联，用于发送中断，从而允许中断在多个I / O通道和处理器之间几乎均匀地加载。而且，可以通过将每个中断与其源处理器相关联的中断相关性方案（即，产生导致中断的I / O请求的处理器）来实现数据位置（“暖缓存”）。

15. 发明申请

US20150293865A1 Restore PCIe Transaction ID On The Fly 审中-公开
标题翻译：在飞行中恢复PCIe事务ID
公开(公告)号：US20150293865A1
公开(公告)日：2015-10-15
申请号：US14728676
申请日：2015-06-02
申请人： Emulex Corporation
发明人： Daming Jin , Vuong Cao Nguyen , Sam Shan-Jan Su , John Sui-Kei Tang , Peter Mark Fiacco
IPC分类号： G06F13/28 , G06F13/38
CPC分类号： G06F13/28 , G06F13/382
摘要： Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again.
摘要翻译：公开了恢复与直接存储器访问（DMA）命令相关联的退出事务标识符（TID），而不等待所有DMA流量终止。记分牌用于跟踪退休的TID，并有选择地恢复退休的TID。 DMA引擎获取TID，并使用它来标记每个DMA请求。如果请求完成，则可以回收TID以用于标记后续请求。但是，如果请求未完成，则TID已退休。可以恢复退出的TID，而不必等待DMA流量结束。任何退休的TID值都可以映射到记分板内的位置。系统中的所有处理器都可以访问读取和清除记分板。清除TID记分板可能会触发DMA引擎恢复映射到该位置的TID，并且可以再次使用TID。

16. 发明授权

US09146808B1 Soft error protection for content addressable memory 有权
标题翻译：内容可寻址存储器的软错误保护
公开(公告)号：US09146808B1
公开(公告)日：2015-09-29
申请号：US13749669
申请日：2013-01-24
申请人： EMULEX CORPORATION
发明人： Jim Butler , Sujith Arramreddy
IPC分类号： G11C29/00 , G06F11/10 , G11C15/04
CPC分类号： G06F12/0815 , G06F11/1064 , G06F11/1076 , G06F2212/1021 , G06F2212/621 , G11C15/00 , G11C15/04
摘要： In one embodiment of the invention, a method for protecting a content addressable memory is disclosed. The method includes storing a marker bit associated with each data block stored in a random access memory (RAM), states of the marker bit representing whether the data block was recently read from the RAM or recently written into the RAM; receiving a client address pointing to a starting address of a data block stored in the RAM; comparing the client address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the client address was stored in the CAM or a miss indicating the client address was not stored in the CAM; and in response to a miss, the method further includes checking a state of the marker bit associated with the data block pointed to by the client address.
摘要翻译：在本发明的一个实施例中，公开了一种用于保护内容可寻址存储器的方法。该方法包括存储与存储在随机存取存储器（RAM）中的每个数据块相关联的标记位，标记位的状态表示数据块是最近从RAM读取还是最近写入RAM中; 接收指向存储在RAM中的数据块的起始地址的客户地址; 将客户端地址与存储在内容可寻址存储器（CAM）中的一个或多个地址进行比较，以确定指示客户端地址的命中被存储在CAM中，或者指示客户端地址未存储在CAM中的未命中; 并且响应于未命中，该方法还包括检查与由客户端地址指向的数据块相关联的标记位的状态。

17. 发明申请

US20150229568A1 Stateless Fibre Channel Sequence Acceleration for Fibre Channel Traffic Over Ethernet 审中-公开
标题翻译：以太网光纤通道流量的无状态光纤通道序列加速
公开(公告)号：US20150229568A1
公开(公告)日：2015-08-13
申请号：US14695212
申请日：2015-04-24
申请人： Emulex Corporation
发明人： Parag Dattatraya BHIDE , Glenn Chih YU , Rahul Korivi SUBRAMANIYAM
IPC分类号： H04L12/803 , H04L29/06 , H04B10/25
CPC分类号： H04L47/125 , H04B10/25 , H04L67/1097 , H04L69/12 , H04L69/22 , H04L69/32
摘要： A method for offloading Fibre Channel transmit data in an I/O operation. The transmit data includes Fibre Channel sequences, each Fibre Channel sequence includes multiple frames. The method includes generating a single transmit sequence request descriptor for transmitting all of the plurality of frames; creating an Ethernet header, a FCoE encapsulation header, and a Fibre Channel header for each frame in response to information in the transmit sequence request descriptor, creating start of frame and end of frame delimiters; inserting data into each frame; computing Fibre Channel CRC and Ethernet FCS for each frame; and transmitting the plurality of frames over a network. In each of the plurality of frames, the Ethernet header precedes the FCoE encapsulation header, which precedes the Fibre Channel header, which precedes the data. The data is followed by the Fibre Channel CRC, which is followed by the Ethernet FCS.
摘要翻译：一种在I / O操作中卸载光纤通道传输数据的方法。发送数据包括光纤通道序列，每个光纤通道序列包括多个帧。该方法包括：生成用于发送所有多个帧的单个发射序列请求描述符; 响应于发送序列请求描述符中的信息为每个帧创建以太网报头，FCoE封装报头和光纤通道报头，创建帧的起始和帧分隔符的结尾; 将数据插入到每个帧中; 计算每个帧的光纤通道CRC和以太网FCS; 以及通过网络发送所述多个帧。在多个帧的每一个中，以太网报头位于先于数据之前的光纤通道报头之前的FCoE封装报头。数据后面是光纤通道CRC，其后是以太网FCS。

18. 发明授权

US08989180B2 RoCE packet sequence acceleration 有权
公开(公告)号：US08989180B2
公开(公告)日：2015-03-24
申请号：US14206640
申请日：2014-03-12
申请人： Emulex Corporation
发明人： Parav Pandit , Masoodur Rahman , Kenny Meng-Hung Wu , Chaitanya Tumuluri
IPC分类号： H04L12/28 , G06F15/173 , G06F13/28 , H04L12/24
CPC分类号： H04L69/22 , G06F13/28 , G06F15/17331 , H04L12/28 , H04L41/06 , Y10T409/308736
摘要： A method, network device and system for remote direct memory access (RDMA) over Converged Ethernet (RoCE) packet sequence acceleration are disclosed. The network device comprises one or more functionality components for communicating with a host system. The host system is configured for implementing a first set of functionalities of a network communication protocol, such as RoCE. The one or more functionality components are also operable to implement a second set of functionalities of the network communication protocol.

19. 发明申请

US20150039884A1 Secure Configuration of Authentication Servers 有权
标题翻译：认证服务器的安全配置
公开(公告)号：US20150039884A1
公开(公告)日：2015-02-05
申请号：US14516205
申请日：2014-10-16
申请人： Emulex Corporation
发明人： Larry Dean Hofer
IPC分类号： H04L29/06
CPC分类号： H04L63/0884 , G06F17/30312 , G06F17/30876 , G06F21/602 , H04L41/0856 , H04L63/0428 , H04L63/08 , H04L63/083 , H04L63/20
摘要： Embodiments of the invention are directed to automatically populating a database of names and secrets in an authentication server by sending one or more lists of one or more names and secrets by a network management software to an authentication server. Furthermore, some embodiments provide that the lists being sent are encrypted and/or embedded in otherwise inconspicuous files.
摘要翻译：本发明的实施例涉及通过网络管理软件将一个或多个名称和秘密的一个或多个列表发送到认证服务器来自动填充认证服务器中的名称和秘密的数据库。此外，一些实施例提供被发送的列表被加密和/或嵌入在其他不显眼的文件中。

20. 发明申请

US20150039839A1 Data Bus Efficiency Via Cache Line Usurpation 有权
标题翻译：数据总线效率通过缓存线占用
公开(公告)号：US20150039839A1
公开(公告)日：2015-02-05
申请号：US14517555
申请日：2014-10-17
申请人： Emulex Corporation
发明人： Steven Gerard LeMire , Vuong Cao Nguyen
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0835 , G06F12/0893 , G06F2212/1024 , G06F2212/1044 , G06F2212/604 , G06F2212/6046 , G06F2212/608 , G06F2212/621
摘要： Embodiments of the current invention permit a user to allocate cache memory to main memory more efficiently. The processor or a user allocates the cache memory and associates the cache memory to the main memory location, but suppresses or bypassing reading the main memory data into the cache memory. Some embodiments of the present invention permit the user to specify how many cache lines are allocated at a given time. Further, embodiments of the present invention may initialize the cache memory to a specified pattern. The cache memory may be zeroed or set to some desired pattern, such as all ones. Alternatively, a user may determine the initialization pattern through the processor.
摘要翻译：本发明的实施例允许用户更有效地向主存储器分配高速缓冲存储器。处理器或用户分配高速缓冲存储器并将缓存存储器与主存储器位置相关联，但是抑制或绕过将主存储器数据读取到高速缓冲存储器中。本发明的一些实施例允许用户指定在给定时间分配多少高速缓存行。此外，本发明的实施例可以将高速缓存存储器初始化为指定的模式。高速缓冲存储器可以被归零或设置为某些期望的模式，例如所有模式。或者，用户可以通过处理器确定初始化模式。

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