专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20060156303A1 Multi-threaded sequenced receive for fast network port stream of packets 有权
标题翻译：多线程排序接收快速网络端口流数据包
公开(公告)号：US20060156303A1
公开(公告)日：2006-07-13
申请号：US11239547
申请日：2005-09-28
申请人： Donald Hooper , Matthew Adiletta , Gilbert Wolrich
发明人： Donald Hooper , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/3851 , G06F9/3885 , G06F9/485 , G06F9/4881 , G06F9/544
摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.
摘要翻译：一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。

12. 发明申请

US20050289514A1 Multi-view history mark with cycle-specific display 审中-公开
标题翻译：具有循环特定显示的多视图历史记录
公开(公告)号：US20050289514A1
公开(公告)日：2005-12-29
申请号：US10877486
申请日：2004-06-25
申请人： Donald Hooper , Eric Walker
发明人： Donald Hooper , Eric Walker
IPC分类号： G06F9/44
CPC分类号： G06F11/3664
摘要： A debugger tool that enables a user to set history marks at selected points in time in a simulation history and to navigate the history marks.
摘要翻译：一种调试工具，使用户能够在模拟历史中选定的时间点设置历史记录，并导航历史记录。

13. 发明申请

US20050198361A1 Method and apparatus for meeting a given content throughput using at least one memory channel 审中-公开
标题翻译：用于使用至少一个存储器通道来满足给定内容吞吐量的方法和装置
公开(公告)号：US20050198361A1
公开(公告)日：2005-09-08
申请号：US10748780
申请日：2003-12-29
申请人： Prashant Chandra , Uday Naik , Alok Kumar , Ameya Varde , Donald Hooper , Debra Bernstein , Myles Wilde , Mark Rosenbluth
发明人： Prashant Chandra , Uday Naik , Alok Kumar , Ameya Varde , Donald Hooper , Debra Bernstein , Myles Wilde , Mark Rosenbluth
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L49/901 , H04L45/125
摘要： A method and apparatus for meeting a given content throughput using at least one memory channel is generally described. In accordance with one example embodiment of the invention, a method to meet a given content throughput using at least one memory channel comprising, comparing the size of at least a portion of received content to a capacity of a single contiguous location within at least one memory channel to meet a given throughput and determining whether to distribute the at least portion of received content across the at least one memory channel, based at least in part, on the comparison.
摘要翻译：通常描述使用至少一个存储器通道来满足给定内容吞吐量的方法和装置。根据本发明的一个示例性实施例，一种使用至少一个存储器信道来满足给定内容吞吐量的方法，包括：将接收的内容的至少一部分的大小与至少一个存储器内的单个连续位置的容量进行比较信道以满足给定的吞吐量并且至少部分地基于比较来确定是否分发穿过所述至少一个存储器信道的接收的内容的至少部分。

14. 发明申请

US20050066256A1 Method and apparatus for performing cyclic redundancy checks 有权
标题翻译：执行循环冗余校验的方法和装置
公开(公告)号：US20050066256A1
公开(公告)日：2005-03-24
申请号：US10666693
申请日：2003-09-18
申请人： Donald Hooper , Matthew Adiletta , Stephanie Hirnak
发明人： Donald Hooper , Matthew Adiletta , Stephanie Hirnak
IPC分类号： G11B20/18 , H03M13/00
CPC分类号： G11B20/1816
摘要： Method and apparatus for performing centralized cyclic redundancy checks (CRC). For one embodiment a current thread of execution compares a connection index with that of a previous thread of execution. If they share the same connection index, a CRC calculation may be performed without providing a CRC residue to a centralized CRC unit since the most recently produced CRC residue by would be associated with a preceding sequential cell of the same packet. For an alternative embodiment a current thread of execution requests a CRC calculation and provides a connection index to the centralized CRC unit, which is used to access a content addressable memory (CAM). A hit in the CAM indicates that the CRC unit may use the CRC residue associated with the connection index in the CAM since it would have resulted from a preceding sequential cell.
摘要翻译：用于执行集中循环冗余校验（CRC）的方法和装置。对于一个实施例，当前的执行线程将连接索引与先前的执行线程的索引进行比较。如果它们共享相同的连接索引，则可以执行CRC计算，而不向集中式CRC单元提供CRC残留，因为最近产生的CRC残留将与相同分组的先前顺序单元相关联。对于替代实施例，当前的执行线程请求CRC计算，并向用于访问内容可寻址存储器（CAM）的集中式CRC单元提供连接索引。 CAM中的命中指示CRC单元可以使用与CAM中的连接索引相关联的CRC残余，因为它将由先前的顺序单元导致。

15. 发明授权

US07111296B2 Thread signaling in multi-threaded processor 失效
标题翻译：线程信令在多线程处理器中
公开(公告)号：US07111296B2
公开(公告)日：2006-09-19
申请号：US10615280
申请日：2003-07-08
申请人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。还描述了用于分组处理的程序线程通信方案。

16. 发明申请

US20050289396A1 Conditional breakpoint using breakpoint function and breakpoint command 审中-公开
标题翻译：使用断点函数和断点命令的条件断点
公开(公告)号：US20050289396A1
公开(公告)日：2005-12-29
申请号：US10877457
申请日：2004-06-25
申请人： Donald Hooper , Eric Walker , Dennis Rivard , William Wheeler , Mark Rosenbluth
发明人： Donald Hooper , Eric Walker , Dennis Rivard , William Wheeler , Mark Rosenbluth
IPC分类号： G06F11/00
CPC分类号： G06F11/3664
摘要： A conditional breakpointing mechanism associates a breakpoint with a location in a program and with a breakpoint function that will be called to execute when the location is reached during a debugging session. The breakpoint function determines if a break will occur. The conditional breakpointing mechanism may used in a multi-threaded, multi-processor simulation environment.
摘要翻译：条件断点机制将断点与程序中的位置以及在调试会话期间到达位置时将被调用执行的断点函数相关联。断点函数确定是否会发生中断。条件断点机制可用于多线程多处理器仿真环境。

17. 发明申请

US20050039182A1 Phasing for a multi-threaded network processor 有权
标题翻译：分阶段的多线程网络处理器
公开(公告)号：US20050039182A1
公开(公告)日：2005-02-17
申请号：US10642053
申请日：2003-08-14
申请人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
发明人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F2209/5018 , H04L69/12
摘要： A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.
摘要翻译：一种用于将数据单元与多线程处理器的线程相关联以用于处理的方法和装置，并且使得每个线程能够在线程执行周期期间对至少两个数据单元执行处理。线程执行周期在各个阶段之间分割，线程处理的每个数据单元都由不同的相位进行处理。

18. 发明申请

US20050038964A1 Folding for a multi-threaded network processor 有权
标题翻译：折叠为多线程网络处理器
公开(公告)号：US20050038964A1
公开(公告)日：2005-02-17
申请号：US10642061
申请日：2003-08-14
申请人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
发明人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F12/0804
摘要： A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.
摘要翻译：使用不同的执行线程和存储器中的公共数据结构来处理与依赖数据流相关联的数据单元的机制。访问存储器中用于处理的公共数据结构使用单个读取操作和单个写入操作。以多个多线程处理阶段的方式折叠多个读 - 修改 - 写存储器操作包括控制第一级，其在与第二级相同的数据单元上操作以将上下文状态信息传递到第二级，用于一致性

19. 发明授权

US06625654B1 Thread signaling in multi-threaded network processor 失效
标题翻译：线程信令在多线程网络处理器中
公开(公告)号：US06625654B1
公开(公告)日：2003-09-23
申请号：US09473799
申请日：1999-12-28
申请人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
发明人： Gilbert Wolrich , Debra Bernstein , Donald Hooper , Matthew J. Adiletta , William Wheeler
IPC分类号： G06F1516
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed than even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个程序线程的多个微启动器。该处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是指向甚至是存储体还是奇数存储器存储器排序存储器引用;以及第二存储器控制器，其基于存储器引用来优化存储器引用被读取引用或写入引用。还描述了用于分组处理的程序线程通信方案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式