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11. 发明申请

US20120261827A1 THROUGH-SILICON VIAS FOR SEMICONDCUTOR SUBSTRATE AND METHOD OF MANUFACTURE 有权
标题翻译：用于半导体基片的半导体六角形及其制造方法
公开(公告)号：US20120261827A1
公开(公告)日：2012-10-18
申请号：US13085668
申请日：2011-04-13
申请人： Chen-Hua YU , Cheng-Hung CHANG , Ebin LIAO , Chia-Lin YU , Hsiang-Yi WANG , Chun Hua CHANG , Li-Hsien HUANG , Darryl KUO , Tsang-Jiuh WU , Wen-Chih CHIOU
发明人： Chen-Hua YU , Cheng-Hung CHANG , Ebin LIAO , Chia-Lin YU , Hsiang-Yi WANG , Chun Hua CHANG , Li-Hsien HUANG , Darryl KUO , Tsang-Jiuh WU , Wen-Chih CHIOU
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/02271 , H01L21/02274 , H01L21/30625 , H01L21/31053 , H01L21/3212 , H01L21/76831 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L23/481 , H01L23/49827 , H01L2225/06541 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.
摘要翻译：半导体部件包括具有顶面的半导体基板。开口从顶表面延伸到半导体衬底中。开口包括内表面。具有第一压缩应力的第一电介质衬垫设置在开口的内表面上。具有拉伸应力的第二电介质衬垫设置在第一电介质衬垫上。具有设置在第二电介质衬垫上的第二压缩应力的第三绝缘衬垫。金属阻挡层设置在第三电介质衬垫上。导电材料设置在金属阻挡层上并填充开口。

12. 发明授权

US08148732B2 Carbon-containing semiconductor substrate 有权
标题翻译：含碳半导体衬底
公开(公告)号：US08148732B2
公开(公告)日：2012-04-03
申请号：US12509339
申请日：2009-07-24
申请人： Chen-Hua Yu , Chia-Lin Yu , Ding-Yuan Chen , Wen-Chih Chiou , Hung-Ta Lin
发明人： Chen-Hua Yu , Chia-Lin Yu , Ding-Yuan Chen , Wen-Chih Chiou , Hung-Ta Lin
IPC分类号： H01L33/00
CPC分类号： H01L33/007 , H01L21/02381 , H01L21/02447 , H01L21/02458 , H01L21/02491 , H01L21/02505 , H01L21/0254 , H01L21/223 , H01L21/26506 , H01L33/025
摘要： A light-emitting diode (LED) device is provided. The LED device is formed on a substrate having a carbon-containing layer. Carbon atoms are introduced into the substrate to prevent or reduce atoms from an overlying metal/metal alloy transition layer from inter-mixing with atoms of the substrate. In this manner, a crystalline structure is maintained upon which the LED structure may be formed.
摘要翻译：提供了一种发光二极管（LED）装置。 LED装置形成在具有含碳层的基板上。将碳原子引入衬底中以防止或减少来自上层金属/金属合金过渡层的原子与衬底的原子的混合。以这种方式，保持可以形成LED结构的晶体结构。

13. 发明授权

US08134163B2 Light-emitting diodes on concave texture substrate 有权
标题翻译：凹面纹理基板上的发光二极管
公开(公告)号：US08134163B2
公开(公告)日：2012-03-13
申请号：US12247895
申请日：2008-10-08
申请人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
发明人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
IPC分类号： H01L33/08
CPC分类号： H01L33/48 , H01L33/20 , H01L33/24
摘要： A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
摘要翻译：提供了一种形成在凹面纹理基板上的发光二极管（LED）的半导体器件。对衬底进行图案化和蚀刻以形成凹陷。沿着凹部的底部形成分离层。沿着侧壁和任选地沿着相邻凹部之间的基板的表面形成LED结构。在这些实施例中，与平面表面相比，LED结构的表面积增加。在另一个实施例中，LED结构形成在凹部内，使得底部接触层与凹部的拓扑不一致。在这些实施例中，硅衬底中的凹陷导致底接触层中的立方结构，例如具有非极性特性并且表现出更高外部量子效率的n-GaN层。

14. 发明申请

US20100068866A1 III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate 有权
标题翻译： III-V族化合物半导体外延从非III-V基片
公开(公告)号：US20100068866A1
公开(公告)日：2010-03-18
申请号：US12539374
申请日：2009-08-11
申请人： Chia-Lin Yu , Chen-Hua Yu , Ding-Yuan Chen , Wen-Chih Chiou
发明人： Chia-Lin Yu , Chen-Hua Yu , Ding-Yuan Chen , Wen-Chih Chiou
IPC分类号： H01L21/768
CPC分类号： H01L21/02365 , H01L21/02104 , H01L21/0237 , H01L21/02381 , H01L21/02458 , H01L21/02491 , H01L21/02502 , H01L21/02538 , H01L21/02639 , H01L21/02642 , H01L21/02645 , H01L29/12
摘要： A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer.
摘要翻译：形成电路结构的方法包括提供基板; 在基板上形成凹部; 在所述基板上形成掩模层，其中所述掩模层覆盖所述基板的非凹部，所述凹部通过所述掩模层中的开口暴露; 在所述凹部中的所述基板的暴露部分上形成缓冲/成核层; 以及从所述凹部生长第III族V族化合物半导体材料，直到从所述凹部生长的所述III-V族化合物半导体材料的部分相互连接形成连续的III-V族化合物半导体层。

15. 发明授权

US08629465B2 Light-emitting diodes on concave texture substrate 有权
标题翻译：凹面纹理基板上的发光二极管
公开(公告)号：US08629465B2
公开(公告)日：2014-01-14
申请号：US13358327
申请日：2012-01-25
申请人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
发明人： Chen-Hua Yu , Hung-Ta Lin , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu
IPC分类号： H01L33/08
CPC分类号： H01L33/48 , H01L33/20 , H01L33/24
摘要： A semiconductor device having light-emitting diodes (LEDs) formed on a concave textured substrate is provided. A substrate is patterned and etched to form recesses. A separation layer is formed along the bottom of the recesses. An LED structure is formed along the sidewalls and, optionally, along the surface of the substrate between adjacent recesses. In these embodiments, the surface area of the LED structure is increased as compared to a planar surface. In another embodiment, the LED structure is formed within the recesses such that the bottom contact layer is non-conformal to the topology of the recesses. In these embodiments, the recesses in a silicon substrate result in a cubic structure in the bottom contact layer, such as an n-GaN layer, which has a non-polar characteristic and exhibits higher external quantum efficiency.
摘要翻译：提供了一种形成在凹面纹理基板上的发光二极管（LED）的半导体器件。对衬底进行图案化和蚀刻以形成凹陷。沿着凹部的底部形成分离层。沿着侧壁和任选地沿着相邻凹部之间的基板的表面形成LED结构。在这些实施例中，与平面表面相比，LED结构的表面积增加。在另一个实施例中，LED结构形成在凹部内，使得底部接触层与凹部的拓扑不一致。在这些实施例中，硅衬底中的凹槽导致底接触层中的立方结构，例如具有非极性特性并且表现出更高外部量子效率的n-GaN层。

16. 发明授权

US08546953B2 Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit 有权
标题翻译：通过硅通孔（TSV）隔离结构降低3D集成电路
公开(公告)号：US08546953B2
公开(公告)日：2013-10-01
申请号：US13324405
申请日：2011-12-13
申请人： Jaw-Juinn Horng , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
发明人： Jaw-Juinn Horng , Chia-Lin Yu , Chung-Hui Chen , Der-Chyang Yeh , Yung-Chow Peng
IPC分类号： H01L23/48 , H01L29/40 , H01L23/04 , H01L21/44
CPC分类号： H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.
摘要翻译：提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

17. 发明授权

US08487410B2 Through-silicon vias for semicondcutor substrate and method of manufacture 有权
公开(公告)号：US08487410B2
公开(公告)日：2013-07-16
申请号：US13085668
申请日：2011-04-13
申请人： Chen-Hua Yu , Cheng-Hung Chang , Ebin Liao , Chia-Lin Yu , Hsiang-Yi Wang , Chun Hua Chang , Li-Hsien Huang , Darryl Kuo , Tsang-Jiuh Wu , Wen-Chih Chiou
发明人： Chen-Hua Yu , Cheng-Hung Chang , Ebin Liao , Chia-Lin Yu , Hsiang-Yi Wang , Chun Hua Chang , Li-Hsien Huang , Darryl Kuo , Tsang-Jiuh Wu , Wen-Chih Chiou
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L21/02271 , H01L21/02274 , H01L21/30625 , H01L21/31053 , H01L21/3212 , H01L21/76831 , H01L21/76832 , H01L21/76844 , H01L21/76846 , H01L23/481 , H01L23/49827 , H01L2225/06541 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

18. 发明授权

US08252682B2 Method for thinning a wafer 有权
标题翻译：减薄晶片的方法
公开(公告)号：US08252682B2
公开(公告)日：2012-08-28
申请号：US12704695
申请日：2010-02-12
申请人： Ku-Feng Yang , Weng-Jin Wu , Hsin-Hsien Lu , Chia-Lin Yu , Chu-Sung Shih , Fu-Chi Hsu , Shau-Lin Shue
发明人： Ku-Feng Yang , Weng-Jin Wu , Hsin-Hsien Lu , Chia-Lin Yu , Chu-Sung Shih , Fu-Chi Hsu , Shau-Lin Shue
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76898 , H01L2224/02372
摘要： A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.
摘要翻译：提供了一种用于薄化晶片的方法。在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。提供晶片载体以附接到晶片的第二侧。晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。此后，绝缘层沉积在隔离层上。然后将绝缘层平坦化以暴露TSV的顶部。电介质层沉积在晶片的平坦化第一侧上。在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。

19. 发明授权

US08138076B2 MOSFETs having stacked metal gate electrodes and method 有权
标题翻译：具有层叠金属栅电极的MOSFET和方法
公开(公告)号：US08138076B2
公开(公告)日：2012-03-20
申请号：US12118919
申请日：2008-05-12
申请人： Cheng-Tung Lin , Yung-Sheng Chiu , Hsiang-Yi Wang , Chia-Lin Yu , Chen-Hua Yu
发明人： Cheng-Tung Lin , Yung-Sheng Chiu , Hsiang-Yi Wang , Chia-Lin Yu , Chen-Hua Yu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/28185 , H01L21/3141 , H01L21/823437 , H01L21/823828 , H01L29/513 , H01L29/517
摘要： MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.
摘要翻译：提供具有层叠金属栅电极的MOSFET及其制造方法。 MOSFET栅电极包括形成在高k栅极电介质层顶上的栅极金属层。通过低氧含量沉积工艺形成金属栅电极而不对晶片衬底进行带电离子轰击。如此形成的金属栅极层的氧含量低，并且可以防止界面氧化层再生长。形成栅极金属层的过程通常避免了对晶片衬底的等离子体损伤。

20. 发明申请

US20120025234A1 Light-Emitting Diode with Textured Substrate 有权
标题翻译：发光二极管与纹理基板
公开(公告)号：US20120025234A1
公开(公告)日：2012-02-02
申请号：US13267701
申请日：2011-10-06
申请人： Chen-Hua Yu , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu , Hung-Ta Lin
发明人： Chen-Hua Yu , Wen-Chih Chiou , Ding-Yuan Chen , Chia-Lin Yu , Hung-Ta Lin
IPC分类号： H01L33/06
CPC分类号： H01L33/22 , H01L33/007 , H01L33/0075 , H01L33/06 , H01L33/24 , H01L33/32
摘要： A light-emitting diode (LED) device is provided. The LED device has raised semiconductor regions formed on a substrate. LED structures are formed over the raised semiconductor regions such that bottom contact layers and active layers of the LED device are conformal layers. The top contact layer has a planar surface. In an embodiment, the top contact layers are continuous over a plurality of the raised semiconductor regions while the bottom contact layers and the active layers are discontinuous between adjacent raised semiconductor regions.
摘要翻译：提供了一种发光二极管（LED）装置。 LED装置已经凸起形成在基板上的半导体区域。在凸起的半导体区域上形成LED结构，使得LED器件的底部接触层和有源层是保形层。顶部接触层具有平坦的表面。在一个实施例中，顶部接触层在多个凸起的半导体区域上是连续的，而底部接触层和有源层在相邻凸起的半导体区域之间是不连续的。

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