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11. 发明申请

US20090235217A1 METHOD TO IDENTIFY TIMING VIOLATIONS OUTSIDE OF MANUFACTURING SPECIFICATION LIMITS 有权
标题翻译：识别制造规范限制之外的时序违规的方法
公开(公告)号：US20090235217A1
公开(公告)日：2009-09-17
申请号：US12045915
申请日：2008-03-11
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Chandramouli Visweswariah
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range.
摘要翻译：评估集成电路设计的方法选择超出制造规范限制的感兴趣的制造参数。然后，该方法对集成电路设计运行定时测试，并且在迭代过程中连续评估定时测试结果，该迭代过程考虑到所选制造参数的时序性能敏感度。该设计使制造范围内的每个参数变得更加健壮。

12. 发明申请

US20080270953A1 IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION 有权
标题翻译： IC芯片功能快速测试与过程覆盖评估
公开(公告)号：US20080270953A1
公开(公告)日：2008-10-30
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译：公开了用于评估IC芯片的方法，系统和程序产品。在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。

13. 发明申请

US20080250370A1 REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS 有权
标题翻译：在数字电路的统计静态时序分析中代表和传播变量电压波形
公开(公告)号：US20080250370A1
公开(公告)日：2008-10-09
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译：描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。

14. 发明申请

US20080209373A1 METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS 失效
标题翻译：基于路径的混合多角度静态时序分析评估统计灵敏度信息的方法和系统
公开(公告)号：US20080209373A1
公开(公告)日：2008-08-28
申请号：US11679251
申请日：2007-02-27
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Peihua Qi , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.
摘要翻译：公开了用于分析集成电路的定时设计的方法，系统和计算机程序产品。根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择通过静态定时测试的静态定时测试点的定时路径; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。

15. 发明申请

US20080072184A1 Method of Achieving Timing Closure in Digital Integrated Circuits by Optimizing Individual Macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的定时闭合的方法
公开(公告)号：US20080072184A1
公开(公告)日：2008-03-20
申请号：US11942034
申请日：2007-11-19
申请人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
发明人： Jun Zhou , David Hathaway , Chandramouli Visweswariah , Patrick Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

16. 发明授权

US07293248B2 System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis 有权
标题翻译：用于在统计静态时序分析中适应非高斯和非线性变化源的系统和方法
公开(公告)号：US07293248B2
公开(公告)日：2007-11-06
申请号：US11056850
申请日：2005-02-11
申请人： Hongliang Chang , Sambasivan Narayan , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Hongliang Chang , Sambasivan Narayan , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.
摘要翻译：提供了一种用于电路的统计时序分析的系统和方法。该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。至少一个参数输入用于接收电路的参数。至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。

17. 发明申请

US20060085775A1 System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis 有权
标题翻译：用于在统计静态时序分析中调节非高斯和非线性变化源的系统和方法
公开(公告)号：US20060085775A1
公开(公告)日：2006-04-20
申请号：US11056850
申请日：2005-02-11
申请人： Hongliang Chang , Sambasivan Narayan , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Hongliang Chang , Sambasivan Narayan , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.
摘要翻译：提供了一种用于电路的统计时序分析的系统和方法。该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。至少一个参数输入用于接收电路的参数。至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。

18. 发明授权

US5886908A Method of efficient gradient computation 失效
标题翻译：高效梯度计算方法
公开(公告)号：US5886908A
公开(公告)日：1999-03-23
申请号：US825278
申请日：1997-03-27
申请人： Andrew Roger Conn , Rudolf Adriaan Haring , Chandramouli Visweswariah
发明人： Andrew Roger Conn , Rudolf Adriaan Haring , Chandramouli Visweswariah
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036 , G06F17/5063
摘要： A method of efficient computation of gradients of a merit function of a system includes the steps of: specifying at least one parameter for which the gradients with respect to the at least one parameter are desired; specifying the merit function of interest in terms of observable measurements of the system; either solving or simulating the system to determine values of the measurements; expressing the gradients of the merit function as the gradient of a weighted sum of measurements; forming an appropriately configured adjoint system; and either solving or simulating the adjoint system to simultaneously determine the gradients of the merit function with respect to the at least one parameter by employing a single adjoint analysis. Preferably, the system may be modeled by a set of equations comprising at least one of the following: a nonlinear set of equations, a linear set of equations, a set of linear partial differential equations, a set of nonlinear partial differential equations, a set of linear differential algebraic equations or a set of nonlinear differential algebraic equations. Further, the system of interest may be a network and, preferably, may be an electrical circuit. Still further, elements of the adjoint network and excitations of the adjoint network are determined in order to obtain the gradients of the merit function by employing a single adjoint analysis. It is to be appreciated that, in a preferred embodiment, the gradients of merit function are computed for the purpose of optimization and the merit function may be either a Lagrangian merit function or an augmented Lagrangian merit function.
摘要翻译：一种有效计算系统的优值函数的梯度的方法包括以下步骤：指定至少一个参数，该参数相对于至少一个参数的梯度是期望的; 根据系统的可观测量指定感兴趣的优点功能; 解决或模拟系统以确定测量值; 将优值函数的梯度表示为加权求和和的梯度; 形成适当配置的伴随系统; 并且通过采用单一伴随分析来解决或模拟伴随系统以同时确定关于至少一个参数的优值函数的梯度。优选地，可以通过包括以下至少一个的一组方程来建模系统：非线性方程组，线性方程组，一组线性偏微分方程，一组非线性偏微分方程，一组的线性微分代数方程或一组非线性微分代数方程。此外，感兴趣的系统可以是网络，并且优选地可以是电路。此外，确定伴随网络的元素和伴随网络的激励，以便通过采用单个伴随分析来获得优值函数的梯度。应当理解，在优选实施例中，为优化目的而计算优值函数的梯度，并且优值函数可以是拉格朗日优值函数或增强的拉格朗日优值函数。

19. 发明授权

US08781792B2 Yield computation and optimization for selective voltage binning 有权
标题翻译：选择性电压合并的产量计算和优化
公开(公告)号：US08781792B2
公开(公告)日：2014-07-15
申请号：US12610291
申请日：2009-10-31
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F11/30
CPC分类号： G06F17/5045 , G06F2217/10 , G06F2217/82
摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.
摘要翻译：提供了用于提高制造芯片的参数芯片产量的技术。在一方面，提供了一种用于优化参数芯片产量的方法。该方法包括以下步骤。基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。然后确定计算的参数芯片产量是否是最佳的。如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。否则，binning方案保持不变。

20. 发明申请

US20140040844A1 Method for Achieving An Efficient Statistical Optimization of Integrated Circuits 有权
标题翻译：实现集成电路高效统计优化的方法
公开(公告)号：US20140040844A1
公开(公告)日：2014-02-06
申请号：US13564751
申请日：2012-08-02
申请人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
发明人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.
摘要翻译：在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。使用统计静态时序分析来分析起始设计，以确定时序违规。检查其统计规范形式的每个时间违规。在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

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