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11. 发明申请

US20220069718A1 SYSTEM AND METHOD FOR CONTROLLING ACTIVE CLAMP FLYBACK CONVERTER 有权
公开(公告)号：US20220069718A1
公开(公告)日：2022-03-03
申请号：US17420866
申请日：2020-06-19
申请人： SOUTHEAST UNIVERSITY , CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Shen XU , Minggang CHEN , Wanqing YANG , Dejin WANG , Rui JIANG , Weifeng SUN , Longxing SHI
IPC分类号： H02M3/335 , H02M1/38
摘要： Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.

12. 发明授权

US11127840B2 Method for manufacturing isolation structure for LDMOS 有权
公开(公告)号：US11127840B2
公开(公告)日：2021-09-21
申请号：US16481576
申请日：2018-07-03
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Shukun Qi , Guipeng Sun
IPC分类号： H01L21/763 , H01L21/473 , H01L29/66 , H01L21/02 , H01L21/311 , H01L21/762
摘要： Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; removing the nitrogen-containing compound side wall residue; and filling the first groove and the second groove with silicon oxide.

13. 发明申请

US20210167190A1 SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20210167190A1
公开(公告)日：2021-06-03
申请号：US16771168
申请日：2018-11-13
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Huajun JIN , Guipeng SUN
IPC分类号： H01L29/66 , H01L29/40 , H01L29/78
摘要： A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

14. 发明申请

US20210043623A1 ANTI-STATIC METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR STRUCTURE 有权
公开(公告)号：US20210043623A1
公开(公告)日：2021-02-11
申请号：US16980368
申请日：2019-03-05
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Jun Sun
IPC分类号： H01L27/07 , H01L29/78 , H01L29/08
摘要： An anti-static metal oxide semiconductor field effect transistor structure includes an anti-static body structure and a slave metal oxide semiconductor field effect transistor, the anti-static body structure includes: a main metal oxide semiconductor field effect transistor; a first silicon controlled rectifier, an anode thereof being connected to a drain of the main metal oxide semiconductor field effect transistor, a cathode and a control electrode thereof being connected to a source of the main metal oxide semiconductor field effect transistor; and a second silicon controlled rectifier, an anode thereof being connected to the drain of the main metal oxide semiconductor field effect transistor, a cathode thereof being connected to a gate of the main metal oxide semiconductor field effect transistor, a control electrode thereof being connected to the source or the gate of the main metal oxide semiconductor field effect transistor.

15. 发明申请

US20210028289A1 TRENCH SPLIT-GATE DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20210028289A1
公开(公告)日：2021-01-28
申请号：US17041980
申请日：2019-03-27
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Dong FANG , Zheng BIAN
IPC分类号： H01L29/423 , H01L29/786 , H01L29/40 , H01L21/285
摘要： A method for manufacturing a trenched split-gate device, comprising: etching a semiconductor substrate to form a trench (120); depositing an oxide in the trench to form a floating-gate oxide layer in which the floating-gate oxide layer gradually thickens from top to bottom along a side wall of the trench, and a thickness of the floating gate oxide layer at a lower part of the side wall of the trench is the same as that of the floating gate oxide layer at a bottom of the trench; depositing polysilicon into the trench to form a floating-gate polysilicon layer (123); growing an insulation medium on an upper surface of the floating-gate polysilicon layer to form an isolation layer (124); and forming a control gate on the isolation layer in the trench.

16. 发明授权

US10816893B2 Method and system for correction of optical proximity effect 有权
公开(公告)号：US10816893B2
公开(公告)日：2020-10-27
申请号：US16305308
申请日：2017-05-26
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Jinyin Wan
IPC分类号： G06F30/00 , G06F30/20 , G06F30/398 , G03F1/36
摘要： A method for correction of an optical proximity effect, comprising: parsing and dividing the periphery of a design pattern to obtain segments to process; for a segment having a corner comprising a segment side (101) and an adjacent side (102) forming a corner relation with the segment side, setting a target point according to the following principle: when the length of the adjacent side (102) is greater than a preset length, the target point is set at the location of the outer end point (104) of the segment side; when the length of the adjacent side (102) is less than or equal to the preset length, the target point is set between the vertex (103) of the corner and the outer end point (104) of the segment side, and the less the length of the adjacent side (102), the further the target point from the location of the outer end point (104); and adjusting, according to a simulation difference of the target point, the design pattern until it conforms to a design target.

17. 发明授权

US10816589B2 Structure and method for testing semiconductor device 有权
公开(公告)号：US10816589B2
公开(公告)日：2020-10-27
申请号：US16474943
申请日：2017-12-26
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Xiaobing Ren , Qun Liu
IPC分类号： G01R31/02 , G01R31/26 , H01L23/544
摘要： A structure for testing a semiconductor device. A first resistor structure (R1) comprises a first active region (110) and a first polysilicon gate (130) disposed on the first active region (110); the width of the first active region (110) is greater than a predetermined width value; the predetermined width value is the critical value of the width of an active region of the semiconductor device when the step height of a shallow trench isolation structure of the semiconductor device affects the width of a polysilicon gate; the design width of the first polysilicon gate (130) is identical to that of the polysilicon gate of the semiconductor device; a second resistor structure (R2) is connected to the first resistor structure (R1) according to a predetermined circuit structure to form a test circuit, and comprises a second active region (210) and a second polysilicon gate (230) disposed on the second active region (210); the width of the second active region (210) is less than the predetermined width value; the design size of the second polysilicon gate (230) is identical to that of the first polysilicon gate (130); the total resistance of a branch circuit where the second resistor structure (R2) is located is equal to the total resistance of a branch circuit where the first resistor structure (R1) is located.

18. 发明授权

US10815122B2 MEMS microphone and preparation method thereof 有权
公开(公告)号：US10815122B2
公开(公告)日：2020-10-27
申请号：US16305119
申请日：2017-05-26
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Yonggang Hu
IPC分类号： B81B7/02 , H04R7/06 , H04R19/04 , B81C1/00
摘要： A MEMS microphone comprises a substrate (110), a lower electrode layer (120), a sacrificial layer (130), a stress layer (140), and an upper electrode layer (150). The substrate (110) is centrally provided with a first opening (111), and the lower electrode layer (120) stretches across the substrate (110). The sacrificial layer (130), the stress layer (140), and the upper electrode layer (150) are sequentially laminated on the lower electrode layer (120), and a second opening (160) is provided on the sacrificial layer (130) and the stress layer (140). The second opening (160) is provided in correspondence with the first opening (111). A stress direction of the stress layer (140) is reverse to a warpage direction of the substrate (110).

19. 发明申请

US20200335607A1 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND INTERGRATED SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20200335607A1
公开(公告)日：2020-10-22
申请号：US16768563
申请日：2018-11-21
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Shikang CHENG , Yan GU , Sen ZHANG
IPC分类号： H01L29/66 , H01L29/78 , H01L27/06 , H01L29/06
摘要： A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

20. 发明申请

US20200216307A1 METHOD FOR MANUFACTURING DUAL-CAVITY STRUCTURE, AND DUAL-CAVITY STRUCTURE 审中-公开
公开(公告)号：US20200216307A1
公开(公告)日：2020-07-09
申请号：US16628001
申请日：2018-07-03
申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.
发明人： Dan Dai , Changfeng Xia , Juanjuan Dong
IPC分类号： B81C1/00 , B81B1/00
摘要： A method for manufacturing a dual-cavity structure and a dual-cavity structure, including: etching on a semiconductor substrate to form a first trench array, tops of the first trench array being separated from each other and bottoms thereof being communicated with each other to form a first cavity; growing a first epitaxial layer on the semiconductor substrate on which the first trench array is formed, to cover the first trench array by the first epitaxial layer; etching on the first epitaxial layer to form a second trench array; tops of the second trench array being separated from each other and bottoms thereof being communicated with each other to form a second cavity; growing a second epitaxial layer on the first epitaxial layer on which the second trench array is formed; and etching the first epitaxial layer and the second epitaxial layer to form a straight groove.

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