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11. 发明申请

US20140317339A1 DATA ACCESS SYSTEM, DATA ACCESSING DEVICE, AND DATA ACCESSING CONTROLLER 审中-公开
标题翻译：数据访问系统，数据访问设备和数据访问控制器
公开(公告)号：US20140317339A1
公开(公告)日：2014-10-23
申请号：US14231832
申请日：2014-04-01
申请人： GENESYS LOGIC, INC.
发明人： Yu-Jen Hsu
IPC分类号： G06F3/06
CPC分类号： G06F3/0658 , G06F3/0604 , G06F3/061 , G06F3/0626 , G06F3/0656 , G06F3/0683 , G06F3/0689
摘要： A data access system, device and controller are provided. The data access system includes a plurality of storage units and first controllers, a second controller, and a host. The first controller is utilized to parallel access the storage units, and each first controller includes a plurality of first storage unit controllers, a buffer and a multiplexer. The first storage unit controllers are coupled one-to-one with the storage units. The multiplexer is coupled to the first storage unit controllers and the buffer. The second controller is coupled to the first controllers. The second controller includes a plurality of second storage unit controllers which are coupled one-to-one with the first controllers. The host is coupled to the second controller, and accesses the storage units through the second controller and the first controllers.
摘要翻译：提供数据访问系统，设备和控制器。数据访问系统包括多个存储单元和第一控制器，第二控制器和主机。第一控制器用于并行访问存储单元，并且每个第一控制器包括多个第一存储单元控制器，缓冲器和多路复用器。第一存储单元控制器与存储单元一对一耦合。多路复用器耦合到第一存储单元控制器和缓冲器。第二控制器耦合到第一控制器。第二控制器包括与第一控制器一对一耦合的多个第二存储单元控制器。主机耦合到第二控制器，并通过第二控制器和第一控制器访问存储单元。

12. 发明授权

US08700839B2 Method for performing static wear leveling on flash memory 有权
标题翻译：在闪存上执行静态损耗均衡的方法
公开(公告)号：US08700839B2
公开(公告)日：2014-04-15
申请号：US11963262
申请日：2007-12-21
申请人： Yuan-Hao Chang , Jen-Wei Hsieh , Tei-Wei Kuo , Cheng-Chih Yang
发明人： Yuan-Hao Chang , Jen-Wei Hsieh , Tei-Wei Kuo , Cheng-Chih Yang
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/02 , G06F3/06
CPC分类号： G06F12/0246 , G06F3/0688 , G06F12/00 , G06F2212/1036 , G06F2212/2022 , G06F2212/222 , G06F2212/7201 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211
摘要： A method for performing a static wear leveling on a flash memory is disclosed. Accordingly, a static wear leveling unit is disposed with a block reclamation unit of either a flash translation layer or a native file system in the flash memory, and utilizes less memory space to trace a distribution status of block leveling cycles of each physical block of the flash memory. Based on the distribution record of the block leveling cycles, the number of the leveling cycles less than a premeditated threshold would be found while the system idles. Then the static wear leveling unit requests the block reclamation unit to level the found blocks. Before leveling the found block, the rarely updated data is compelled to move from one block to another block which is leveled frequently, whereby accurate wear leveling cycles for the blocks can be averaged extremely.
摘要翻译：公开了一种用于在闪速存储器上执行静态损耗均衡的方法。因此，静态损耗均衡单元在闪速存储器中设置有闪存转换层或本地文件系统的块回收单元，并且利用较少的存储空间来跟踪每个物理块的块调平周期的分布状态闪存根据块调平周期的分布记录，当系统空转时，会发现小于预谋阈值的调平周期数。然后，静态磨损均衡单元请求块回收单元对找到的块进行调平。在调平找到的块之前，很少更新的数据被迫从一个块移动到另一个频繁调平的块，从而可以极大地平均块的精确损耗平衡周期。

13. 发明申请

US20140098260A1 METHOD FOR PROCESSING IMAGE DATA 有权
标题翻译：处理图像数据的方法
公开(公告)号：US20140098260A1
公开(公告)日：2014-04-10
申请号：US14045470
申请日：2013-10-03
申请人： GENESYS LOGIC, INC.
发明人： Wen-fu TSAI
IPC分类号： H04N9/79
CPC分类号： H04N9/79 , H04N5/225 , H04N5/23229
摘要： A method for processing image data is described. The method includes the steps: (a) fully writing image data into first buffer area; (b) vertically reading the image data in first buffer area and horizontally writing image data into second buffer area; (c) while completely reading a first portion of first buffer area, allocating the complete read first portion of first buffer area to second buffer area to be served as a writing section; (d) vertically reading the image data in a second portion of first buffer area and writing the image data into second buffer area; and (e) vertically reading the image data of second buffer area and horizontally writing the image data into first buffer area, and after completely reading a portion of second buffer area, allocating the read portion of second buffer area to first buffer area.
摘要翻译：描述用于处理图像数据的方法。该方法包括以下步骤：（a）将图像数据完全写入第一缓冲区; （b）垂直读取第一缓冲区域中的图像数据，并将图像数据水平地写入第二缓冲区域; （c）在完全读取第一缓冲区的第一部分的同时，将第一缓冲区的完整读取第一部分分配给要作为写入部分的第二缓冲区; （d）垂直读取第一缓冲区域的第二部分中的图像数据并将图像数据写入第二缓冲区域; 以及（e）垂直读取第二缓冲区域的图像数据并将图像数据水平地写入第一缓冲区域，并且在完全读取第二缓冲区域的一部分之后，将第二缓冲区域的读取部分分配给第一缓冲区域。

14. 发明申请

US20130013936A1 DYNAMIC POWER MANAGEMENT SYSTEM FOR UNIVERSAL SERIAL BUS (USB) HUB AND METHOD THEREOF 有权
标题翻译：用于通用串行总线（USB）集线器的动态电源管理系统及其方法
公开(公告)号：US20130013936A1
公开(公告)日：2013-01-10
申请号：US13244320
申请日：2011-09-24
申请人： Chih-Jung Lin , Wei-te Lee
发明人： Chih-Jung Lin , Wei-te Lee
IPC分类号： G06F1/26
CPC分类号： G06F1/266
摘要： A dynamic power management system for USB hub and method thereof are described. The dynamic power management system includes a host device, a power unit and a hub device. A power management module disposed in the hub device dynamically adjusts the power-supplying statuses of ports in the hub device and further reduces the cost of power transformer externally connected to the hub device.
摘要翻译：描述了用于USB集线器的动态电源管理系统及其方法。动态电源管理系统包括主机设备，电源单元和集线器设备。设置在集线器装置中的电源管理模块动态地调整集线器装置中的端口的供电状态，并进一步降低外部连接到集线器装置的电力变压器的成本。

15. 发明授权

US08345322B2 Scanning apparatus having dual power mode 有权
标题翻译：具有双功率模式的扫描设备
公开(公告)号：US08345322B2
公开(公告)日：2013-01-01
申请号：US12546887
申请日：2009-08-25
申请人： Tsu-hsun Yi , Mi-lai Tsai
发明人： Tsu-hsun Yi , Mi-lai Tsai
IPC分类号： H04N1/04 , H04N1/32
CPC分类号： H04N1/00885 , H04N1/00204 , H04N1/00899 , H04N1/00901 , H04N1/00907 , H04N2201/0041 , H04N2201/0049 , Y10T307/50
摘要： A scanning apparatus having dual power mode is described. The scanning apparatus includes a detection module, a switch unit, and a power controller. The detection module detects a first voltage signal and a second voltage signal for generating a detecting signal. The switch unit receives the commands from the power controller for outputting the first voltage signal and/or the second voltage signal to the image acquiring device of the scanning apparatus. The power controller determines whether the first voltage signal is detected according to the detecting signal. While the first voltage signal is detected, the power controller controls the switch unit to output the first voltage signal and/or the second voltage signal to the image acquiring device. While the first voltage signal is not exist, the power controller controls the switch unit to output the second voltage signal to the image acquiring device.
摘要翻译：描述具有双功率模式的扫描装置。扫描装置包括检测模块，开关单元和功率控制器。检测模块检测用于产生检测信号的第一电压信号和第二电压信号。开关单元从功率控制器接收用于将第一电压信号和/或第二电压信号输出到扫描装置的图像获取装置的命令。功率控制器根据检测信号确定是否检测到第一电压信号。当检测到第一电压信号时，功率控制器控制开关单元将第一电压信号和/或第二电压信号输出到图像获取装置。当不存在第一电压信号时，功率控制器控制开关单元将第二电压信号输出到图像获取装置。

16. 发明授权

US08140882B2 Serial bus clock frequency calibration system and method thereof 有权
标题翻译：串行总线时钟频率校准系统及其方法
公开(公告)号：US08140882B2
公开(公告)日：2012-03-20
申请号：US12388373
申请日：2009-02-18
申请人： Wei-te Lee , Shin-te Yang , Yen-fah Chu
发明人： Wei-te Lee , Shin-te Yang , Yen-fah Chu
IPC分类号： H03D3/24
CPC分类号： G06F1/12 , H03L7/087 , H03L7/113 , H04L7/033 , H04L7/046 , H04L7/10
摘要： A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.
摘要翻译：本文公开了串行总线时钟频率校准系统及其方法。该系统利用第一频率校准装置和第二频率校准装置来共享振荡器，以便执行用于产生不同频率调谐范围的两级时钟频率分辨率校准。这可以带来最佳的频率分辨率，并大大降低系统复杂性并节省元件成本。

17. 发明授权

US07975095B2 Device and method for using a flash memory as a hard disk cache 有权
标题翻译：使用闪存作为硬盘缓存的设备和方法
公开(公告)号：US07975095B2
公开(公告)日：2011-07-05
申请号：US11963173
申请日：2007-12-21
申请人： Jen-Wei Hsieh , Po-Liang Wu , Yuan-Hao Chang , Tei-Wei Kuo , Cheng-Chih Yang
发明人： Jen-Wei Hsieh , Po-Liang Wu , Yuan-Hao Chang , Tei-Wei Kuo , Cheng-Chih Yang
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/222
摘要： A cache device comprises a hard disk, cache control unit and at least one flash memory, whereby the cache control unit controlling and regulating the flash memory as the hard disk cache device. The present invention method is defined by setting up a management table to manage each corresponding logical block address of the flash memory through a cache data read-out step and cache data write-in step in order to manage the cache read or write action of the flash memory on the hard disk. In addition, the step of recycling a cache space and replacing cache temporary data storage is to remove and replace temporary cache and storage space within the flash memory on the hard disk. Moreover, the step of reconstruction management table is provided to reconstruct management table loss or damage caused by power outage or irregular shut-down of the computer and will be able to provide flash memory on the hard disk cache control.
摘要翻译：缓存装置包括硬盘，高速缓存控制单元和至少一个闪速存储器，由此高速缓存控制单元控制和调节闪存作为硬盘高速缓存设备。通过设置管理表来定义本发明的方法，以通过高速缓存数据读出步骤和高速缓存数据写入步骤来管理闪存的每个对应的逻辑块地址，以便管理高速缓存读取或写入动作闪存在硬盘上。此外，回收高速缓存空间和替换高速缓存临时数据存储的步骤是删除和替换硬盘中的闪存中的临时高速缓存和存储空间。此外，重建管理表提供了重建管理表丢失或由电源中断或计算机不规则关闭造成的损坏，并能够在硬盘缓存控制上提供闪存。

18. 发明申请

US20110080534A1 LIGHT COMPENSATION SCHEME, OPTICAL MACHINE DEVICE, DISPLAY SYSTEM AND METHOD FOR LIGHT COMPENSATION 有权
标题翻译：光补偿方案，光机装置，显示系统和轻量补偿方法
公开(公告)号：US20110080534A1
公开(公告)日：2011-04-07
申请号：US12642459
申请日：2009-12-18
申请人： Nei-Chiung Perng , Chih-nan Wei , Po-Yao Chuang
发明人： Nei-Chiung Perng , Chih-nan Wei , Po-Yao Chuang
IPC分类号： G02F1/13363
CPC分类号： G02F1/1336 , G02F1/136277 , G02F2001/133622 , G02F2201/58 , G09G3/3413 , G09G2310/0235 , G09G2320/0233 , G09G2320/0626 , G09G2320/0646 , G09G2360/145 , H04N9/3111 , H04N9/3155
摘要： A light compensation scheme, an optical machine device, a display system and a method for light compensation are disclosed herein. The light compensation scheme includes a detector for inspecting a data related to a luminous flux of each of different color beams, and a controller for selectively adjusting anytime a luminosity of at least one of a plurality of pointolites and/or the transmittances of at least one part of liquid crystals disposed within a liquid crystal display panel, based on the inspected data.
摘要翻译：本文公开了光补偿方案，光学机器装置，显示系统和光补偿方法。所述光补偿方案包括检测器，用于检查与每个不同颜色光束的光通量有关的数据;以及控制器，用于随时选择性地调整多个波斯坦托耳中的至少一个的光度和/或至少一个波特率的透射率基于检查数据，配置在液晶显示面板内的液晶的一部分。

19. 发明授权

US07890693B2 Flash translation layer apparatus 有权
标题翻译：闪存转换层设备
公开(公告)号：US07890693B2
公开(公告)日：2011-02-15
申请号：US12018346
申请日：2008-01-23
申请人： Cheng-chih Yang , Tei-wei Kuo , Chin-hsien Wu
发明人： Cheng-chih Yang , Tei-wei Kuo , Chin-hsien Wu
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.
摘要翻译：公开了一种闪光转换层设备。闪存转换层设备分别耦合到闪速存储器和读写控制器。闪存转换层装置包括指令寄存器，逻辑地址寄存器，数据寄存器，第一辅助控制器，微处理器，地址转换单元，第二辅助控制器，闪存地址寄存器和可调平移层单元。此外，可调翻译层单元将块视为粗粒度地址转换表的单位，并将页面分别视为细粒度地址转换表的单位。因此，本发明可以提供减少空数据收集过程的空间和时间的能力，并且当逻辑地址对应于物理地址时提高效率。

20. 发明申请

US20110016261A1 PARALLEL PROCESSING ARCHITECTURE OF FLASH MEMORY AND METHOD THEREOF 审中-公开
标题翻译：闪存存储器的并行处理架构及其方法
公开(公告)号：US20110016261A1
公开(公告)日：2011-01-20
申请号：US12554197
申请日：2009-09-04
申请人： Jin-min Lin , Wei-kan Hwang
发明人： Jin-min Lin , Wei-kan Hwang
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7208
摘要： A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel.
摘要翻译：描述了闪速存储器的并行处理架构及其方法。处理单元分类多个命令以分别生成第一命令组和第二命令组。处理单元执行第一命令组和第二命令组。第一控制单元执行第一命令组以访问存储在第一存储单元中的数据，第二控制单元同时执行第二命令组以访问存储在第二存储单元中的数据，以处理存储在第一存储单元中的数据，第二个存储单元并行。

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