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11. 发明授权

US06961863B2 Techniques for facilitating conversion between asynchronous and synchronous domains 失效
标题翻译：促进异步和同步域之间转换的技术
公开(公告)号：US06961863B2
公开(公告)日：2005-11-01
申请号：US10281424
申请日：2002-10-25
申请人： Michael I. Davies , Andrew Lines , Robert Southworth
发明人： Michael I. Davies , Andrew Lines , Robert Southworth
IPC分类号： G06F12/00 , G06F1/12 , G06F13/40 , G06F13/42 , H04L7/00 , H04L12/56
CPC分类号： G06F13/4059
摘要： An interface for use between an asynchronous domain and a synchronous domain is described. The asynchronous domain is characterized by transmission of data in accordance with a delay-insensitive handshake protocol. The synchronous domain is characterized by transmission of data in accordance with transitions of a clock signal. The interface includes a datapath operable to transfer a data token between the domains. The interface also includes control circuitry operable to enable transfer of the data token via the datapath in response to a transition of the clock signal and at least one completion of the handshake protocol.
摘要翻译：描述了在异步域和同步域之间使用的接口。异步域的特征在于根据延迟不敏感的握手协议传输数据。同步域的特征在于根据时钟信号的转变传输数据。该接口包括可用于在域之间传输数据令牌的数据路径。接口还包括控制电路，其可操作以响应于时钟信号的转变和至少一个握手协议的完成，经由数据路径传送数据令牌。

12. 发明申请

US20040151209A1 Asynchronous system-on-a-chip interconnect 有权
标题翻译：异步片上系统互连
公开(公告)号：US20040151209A1
公开(公告)日：2004-08-05
申请号：US10634597
申请日：2003-08-04
申请人： Fulcrum Microsystems Inc. A California Corporation
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04J003/06
CPC分类号： G06F13/423 , G06F1/12 , G06F2213/0038 , H04L7/005 , H04L7/02 , H04L49/101 , H04L2012/5674 , H04Q3/0004 , H04Q2213/13034 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/13361 , H04Q2213/13362
摘要： Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
摘要翻译：描述了涉及包括多个同步模块的片上系统的方法和装置，每个同步模块具有由数据速率表征的相关联的时钟域，数据速率包括多个不同的数据速率。片上系统还包括多个时钟域转换器。每个时钟域转换器被耦合到对应的一个同步模块，并且可操作以在对应的同步模块的时钟域和根据异步握手协议的数据传输特征的异步域之间转换数据。异步交叉开关耦合到多个时钟域转换器，并且可在异步域中操作以实现任何两个时钟域转换器之间的先进先出（FIFO）通道，从而促进任何两个时钟域转换器之间的通信同步模块。

13. 发明申请

US20030146075A1 Asynchronous crossbar with deterministic or arbitrated control 有权
标题翻译：具有确定性或仲裁控制的异步交叉开关
公开(公告)号：US20030146075A1
公开(公告)日：2003-08-07
申请号：US10237406
申请日：2002-09-06
申请人： Fulcrum Microsystems Inc.
发明人： Uri Cummings , Andrew Lines
IPC分类号： H01H009/00
CPC分类号： H04Q3/0004
摘要： Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.
摘要翻译：描述了涉及可操作以根据路由控制信息将数据从第一数量的输入信道中的任何一个路由到第二数量的输出信道中的任一个的交叉开关的方法和装置。输入通道和输出通道的每个组合对应于多个链接中的一个。交叉开关电路可操作地以确定性的方式在每个链路上路由数据，从而保留由路由控制信息表示的部分排序。不同链接的事件是不相关的。

14. 发明授权

US08086975B2 Power aware asynchronous circuits 失效
标题翻译：功率感知异步电路
公开(公告)号：US08086975B2
公开(公告)日：2011-12-27
申请号：US12421963
申请日：2009-04-10
申请人： Ken Shiring , Peter A. Beerel , Andrew Lines , Arash Saifhashemi
发明人： Ken Shiring , Peter A. Beerel , Andrew Lines , Arash Saifhashemi
IPC分类号： G06F17/50
CPC分类号： G06F17/5059
摘要： Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.
摘要翻译：描述了用于将诸如组合模块，触发器（或锁存器）和时钟门控模块的同步电路的网表转换为异步模块的网表的技术。描述包括算法的过程，其中包括启用域中的多个模块，以便仅当启用域的传入启用令牌具有UPDATE值时才激活它们。这些模块可以集群到启用域内，以便每个集群都有一个单独的控制器。捆绑和聚类的目标功能可以使给定周期时间的功耗最小化。示例性实施例可以包括门控多级多米诺骨牌模板。

15. 发明授权

US08051396B2 Logic synthesis of multi-level domino asynchronous pipelines 有权
标题翻译：多级多米诺异步管道逻辑综合
公开(公告)号：US08051396B2
公开(公告)日：2011-11-01
申请号：US12435270
申请日：2009-05-04
申请人： Peter Beerel , Andrew Lines , Michael Davies
发明人： Peter Beerel , Andrew Lines , Michael Davies
IPC分类号： G06F17/50
CPC分类号： G06F17/5059
摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
摘要翻译：描述了用于优化电路设计的方法和装置。产生对应于电路设计的门级电路描述。门级电路描述包括跨越多个级别的多条管道。使用线性编程技术，将最少数量的缓冲区添加到选定的管道中，使得满足性能约束。

16. 发明授权

US07916718B2 Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics 有权
标题翻译：交换机结构中的流量和拥塞控制，用于多跳，高速存储器面板
公开(公告)号：US07916718B2
公开(公告)日：2011-03-29
申请号：US11737511
申请日：2007-04-19
申请人： Zhi-Hern Loh , Michael Davies , Uri Cummings
发明人： Zhi-Hern Loh , Michael Davies , Uri Cummings
IPC分类号： H04L12/50
CPC分类号： H04L47/10 , H04L45/302 , H04L47/11 , H04L47/125 , H04L49/103 , H04L49/205 , H04L49/254 , H04L49/508
摘要： A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.
摘要翻译：描述共享存储器交换机和交换矩阵体系结构，其使用共享存储器的分区来实现多个独立的虚拟拥塞域，从而允许独立地针对不同类别的业务处理拥塞。

17. 发明申请

US20090288059A1 CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS 有权
标题翻译：非线性电路的聚类和扇区优化
公开(公告)号：US20090288059A1
公开(公告)日：2009-11-19
申请号：US12429772
申请日：2009-04-24
申请人： Georgios Dimou , Peter A. Beerel , Andrew Lines
发明人： Georgios Dimou , Peter A. Beerel , Andrew Lines
IPC分类号： G06F17/50
CPC分类号： G06F9/3869 , G06F17/5059
摘要： Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.
摘要翻译：描述了用于通过将合成门自动聚集到流水线阶段中以从同步电路的任何任意HDL表示生成异步电路的技术，该流水线阶段松弛匹配以满足性能目标同时最小化面积。可以提供自动流水线，其中总体设计的吞吐量不限于原始RTL规范中的时钟频率或流水线级别。这些技术适用于许多异步设计风格。可以设计一个模型和基础设施，指导群集，以避免引入死锁并实现目标电路性能。松弛匹配模型可用于利用提升结果质量的缓冲树的优化。

18. 发明申请

US20090217232A1 LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES 有权
标题翻译：多层次多米诺非线性管道的逻辑综合
公开(公告)号：US20090217232A1
公开(公告)日：2009-08-27
申请号：US12435270
申请日：2009-05-04
申请人： Peter Beerel , Andrew Lines , Michael Davies
发明人： Peter Beerel , Andrew Lines , Michael Davies
IPC分类号： G06F17/50
CPC分类号： G06F17/5059
摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
摘要翻译：描述了用于优化电路设计的方法和装置。产生对应于电路设计的门级电路描述。门级电路描述包括跨越多个级别的多条管道。使用线性编程技术，将最少数量的缓冲区添加到选定的管道中，使得满足性能约束。

19. 发明申请

US20080181103A1 TRAFFIC DISTRIBUTION TECHNIQUES 有权
标题翻译：交通分配技术
公开(公告)号：US20080181103A1
公开(公告)日：2008-07-31
申请号：US11668133
申请日：2007-01-29
申请人： Michael Davies
发明人： Michael Davies
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/125
摘要： Methods and apparatus are described for assigning data units to a plurality of groups. A key is generated for each of the data units such that the keys corresponding to associated ones of the data units are identical. An initial hash value is generated for each of the keys. A number of techniques are described for then deterministically scrambling the initial hash values such that small bit changes in the keys will typically produce stochastically large changes in the final hash values. The data units are mapped to specific ones of the groups with reference to the scrambled hash values.
摘要翻译：描述了将数据单元分配给多个组的方法和装置。为每个数据单元生成一个密钥，使得与相关数据单元相对应的密钥相同。为每个键生成一个初始哈希值。描述了许多技术，用于确定性地扰乱初始散列值，使得密钥中的小位改变通常将在最终散列值中产生随机变化。参考加扰散列值将数据单元映射到组中的特定组。

20. 发明申请

US20060120189A1 Logic synthesis of multi-level domino asynchronous pipelines 失效
公开(公告)号：US20060120189A1
公开(公告)日：2006-06-08
申请号：US11271323
申请日：2005-11-10
申请人： Peter Beerel , Andrew Lines , Michael Davies
发明人： Peter Beerel , Andrew Lines , Michael Davies
IPC分类号： G11C7/00
CPC分类号： G06F17/5059
摘要： Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.

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