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181. 发明授权

US5392441A Pump bus to avoid indeterminacy in reading variable bit field 失效
标题翻译：泵总线，以避免读取可变位字段的不确定性
公开(公告)号：US5392441A
公开(公告)日：1995-02-21
申请号：US143529
申请日：1993-10-26
申请人： Gary L. Brasher , James H. Nuckols , Jeffrey S. Watters
发明人： Gary L. Brasher , James H. Nuckols , Jeffrey S. Watters
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4072 , G06F13/4217
摘要： A data field having a variable number of zero-level bits is read by a bus in a digital system, wherein the bus is pumped by writing all logical "one" bits onto the bus lines just before they are read. The unused bits will then be still in a logical "one" state, i.e. a known value, rather than floating or at an indeterminate value. A program for performing this operation in a computer uses steps to prevent other operations such as refresh cycles or interrupts from being interposed between the write and read cycles. A CPU may use this method to read a system identifier value upon boot-up, for example.
摘要翻译：具有可变数量的零电平位的数据字段由数字系统中的总线读取，其中通过在读取总线之前将所有逻辑“1”位写入总线来泵送总线。然后，未使用的位将仍然处于逻辑“一”状态，即已知值，而不是浮动或不确定值。用于在计算机中执行该操作的程序使用步骤来防止诸如刷新周期或中断之类的其他操作被插入在写周期和读周期之间。例如，CPU可以使用该方法在启动时读取系统标识符值。

182. 发明授权

US5305277A Data processing apparatus having address decoder supporting wide range of operational frequencies 失效
标题翻译：具有地址解码器的数据处理装置支持宽范围的工作频率
公开(公告)号：US5305277A
公开(公告)日：1994-04-19
申请号：US690738
申请日：1991-04-24
申请人： Michael T. Derwin , Brenda M. Ozaki , William A. Wall
发明人： Michael T. Derwin , Brenda M. Ozaki , William A. Wall
IPC分类号： G06F13/42 , G11C7/00
CPC分类号： G06F13/4217
摘要： An address decoder is connected to an address bus and comprises a plurality of latches for latching address signals from the address bus. Decode logic is connected to use unlatched addresses from the address bus or latched addresses from the latches. The decoder is selectively operable to decode addresses in two modes, an unlatched mode and a latched mode dependent upon system frequency. The decode logic produces a signal that is transmitted into a state machine for controlling operation thereof.
摘要翻译：地址解码器连接到地址总线，并且包括用于锁存来自地址总线的地址信号的多个锁存器。连接解码逻辑以从地址总线中使用未锁定的地址或从锁存器锁存地址。解码器选择性地可操作以解码两种模式中的地址，取决于系统频率的解锁模式和锁存模式。解码逻辑产生被传送到状态机中以控制其操作的信号。

183. 发明授权

US5255370A Data transfer apparatus and data transfer system 失效
标题翻译：数据传输设备和数据传输系统
公开(公告)号：US5255370A
公开(公告)日：1993-10-19
申请号：US295947
申请日：1988-12-28
申请人： Kazuya Sako , Masaaki Nagami , Takeshi Chono , Shoji Fujimoto , Katsumaro Yasui
发明人： Kazuya Sako , Masaaki Nagami , Takeshi Chono , Shoji Fujimoto , Katsumaro Yasui
IPC分类号： G06F13/38 , G06F13/42 , H04S5/02 , G06F13/00
CPC分类号： H04S5/02 , G06F13/38 , G06F13/4217 , H04S3/02 , H04S5/005
摘要： When transferring digital signals between plural electronic devices, there is a case of transferring data differing in the number of bits using the same structure. In this case, plural kinds of structure corresponding to the number of the bits are needed, and the apparatus becomes large and complicated. The data transfer apparatus of the present invention is capable of transferring data differing in the number of bits easily using the same structure, by the efficient use of constituent elements in every aspect of data transfer and processing and time sharing techniques.
摘要翻译： PCT No.PCT / JP88 / 00430 Sec。 371日期：1988年12月28日第 102（e）日期1988年12月28日PCT提交1988年4月28日PCT公布。出版物WO88 / 08574 日期：1988年11月3日。当在多个电子设备之间传送数字信号时，存在使用相同结构传送位数不同的数据的情况。在这种情况下，需要与位数相对应的多种结构，并且装置变大而复杂。本发明的数据传送装置能够通过在数据传送和处理以及时间分配技术的各个方面有效地使用构成要素，以相同的结构容易地传送位数不同的数据。

184. 发明授权

US5235684A System bus having multiplexed command/ID and data 失效
标题翻译：具有多路复用命令/ ID和数据的系统总线
公开(公告)号：US5235684A
公开(公告)日：1993-08-10
申请号：US213402
申请日：1988-06-30
申请人： Robert D. Becker , Martin J. Schwartz , Kevin H. Curcuru
发明人： Robert D. Becker , Martin J. Schwartz , Kevin H. Curcuru
IPC分类号： G06F13/36 , G06F12/08 , G06F13/42
CPC分类号： G06F13/4217 , G06F12/0833 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A system bus 12 for an information processing system 10 includes a first group of signal lines 16 whereon command/ID information is time multiplexed with data, and a second group of signal lines 14 for conveying address information. During a first bus cycle command/ID information is presented on the first group of signal lines while the address is presented on the second group of signal lines. During a subsequent bus cycle, and for a data write or data return operation, the first group of signal lines conveys data. Other bus connections, such as cache memories, are thus apprised of the address a full bus cycle before the data is presented thereby providing the bus connections with sufficient time to decode and otherwise operate on the bus information. Multiple word data returns from a system memory are characterized as having the address associated with a particular word of data presented in the immediately prior bus cycle, facilitating the pipelining of data and address information through the system bus. The dual functionality of the first group of signal lines eliminates the requirement for separate and dedicated command/ID and data signal line paths and associated driving and receiving circuit elements.
摘要翻译：用于信息处理系统10的系统总线12包括第一组信号线16，其中命令/ ID信息与数据进行时间复用，以及第二组信号线14，用于传送地址信息。在第一个总线周期命令期间，ID信息被呈现在第一组信号线上，而地址被呈现在第二组信号线上。在随后的总线周期期间，并且对于数据写入或数据返回操作，第一组信号线传送数据。因此，在呈现数据之前，其他总线连接（例如高速缓冲存储器）被告知地址一个完整的总线周期，从而为总线连接提供足够的时间来解码和以其它方式对总线信息进行操作。来自系统存储器的多个字数据返回的特征在于具有与紧接在前的总线周期中呈现的特定数据字相关联的地址，便于通过系统总线流水线数据和地址信息。第一组信号线的双重功能消除了对单独和专用命令/ ID和数据信号线路径以及相关联的驱动和接收电路元件的要求。

185. 发明授权

US5121487A High speed bus with virtual memory data transfer capability using virtual address/data lines 失效
标题翻译：具有虚拟存储器数据传输能力的高速总线使用虚拟地址/数据线
公开(公告)号：US5121487A
公开(公告)日：1992-06-09
申请号：US313250
申请日：1989-02-21
申请人： Andreas Bechtolsheim
发明人： Andreas Bechtolsheim
IPC分类号： G06F12/10 , G06F13/36 , G06F13/364 , G06F13/42
CPC分类号： G06F13/4217 , G06F13/36 , G06F13/364 , Y02B60/1228 , Y02B60/1235
摘要： An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.
摘要翻译：公开了一种具有虚拟存储能力的改进的高速数据传输总线。总线在采用外围设备的计算机系统中具有特殊应用。总线允许通过使用虚拟内存方案进行高速数据传输。此外，本发明使实现总线所需的线路数量最小化。本发明还使特定设备在访问总线并完成数据传输之前需要等待的时间量最小化。此外，本发明采用驱动有源和无源的控制信号，便于将总线连接到低功率CMOS技术。

186. 发明授权

US5109490A Data transfer using bus address lines 失效
标题翻译：使用总线地址线进行数据传输
公开(公告)号：US5109490A
公开(公告)日：1992-04-28
申请号：US297772
申请日：1989-01-13
申请人： Ravi K. Arimilli , Sudhir Dhawan , James O. Nicholson , David W. Siegel
发明人： Ravi K. Arimilli , Sudhir Dhawan , James O. Nicholson , David W. Siegel
IPC分类号： G06F13/28 , G06F13/42
CPC分类号： G06F13/4217 , G06F13/28
摘要： A computer system can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

187. 发明授权

US5101347A System for reducing skew in the parallel transmission of multi-bit data slices 失效
标题翻译：用于减少并行传输多位数据片的系统
公开(公告)号：US5101347A
公开(公告)日：1992-03-31
申请号：US272589
申请日：1988-11-16
申请人： Ramanatha V. Balakrishnan , Desmond W. L. Young
发明人： Ramanatha V. Balakrishnan , Desmond W. L. Young
IPC分类号： G06F13/42
CPC分类号： G06F13/4217
摘要： A system for reducing skew in the parallel transmission of digital data slices is provided. The system includes a transmitter unit comprising a plurality of transmitter memory devices. Control logic provides a strobe signal to each transmitter unit memory device to implement the transfer of a desired number of data characters from the transmitter unit to a receiver unit. Both its associated data slice and the strobe signal are transferred from each transmitter unit memory device to the bus via an associated transmitter unit bus driver. Each data slice and its associated strobe signal are then transferred from the bus to a corresponding receiver unit memory device via a corresponding receiver unit bus receiver device. Each receiver unit memory device includes means for generating a "receiver-full" status signal that indicates that all data slices transferred from the corresponding transmitter unit memory device have been received. These "receiver-full" status signals are monitored and a "transfer-done" status signal is issued when all data slices transferred from the transmitter unit have been received by the receiver unit. Skew within a particular transmission path is compensated for by providing a controlled delay path for the clock signal in each device within that path.

188. 发明授权

US5023870A Interface circuit for data transmission between a microprocessor system and a time-division-multiplexed system 失效
标题翻译：接口电路，用于微处理器系统和时分复用系统之间的数据传输
公开(公告)号：US5023870A
公开(公告)日：1991-06-11
申请号：US369885
申请日：1989-06-22
申请人： Han Kem
发明人： Han Kem
IPC分类号： G06F13/376 , G06F13/42 , H04L29/06
CPC分类号： G06F13/376 , G06F13/4217 , H04L29/06
摘要： The circuit of the present invention provides a signal which allows data to be transferred between a first synchronous system to a second synchronous system. Where the first synchronous system is a Time-Division-Multiplexing (TDM) system and the second synchronous system is a Microprocessor system. The transfer is allowed at the end of the assigned time slot provided that the microprocessor is not accessing the data. If the microprocessor is accessing the data, then the transfer is delayed for three clock cycles of the TDM clock. After the delay, if the microprocessor is still accessing the data, the transfer is delayed again. The delaying continues until the microprocessor is no longer accessing the data, at which time the transfer is allowed.
摘要翻译：本发明的电路提供了允许数据在第一同步系统与第二同步系统之间传输的信号。其中第一同步系统是时分多路复用（TDM）系统，第二同步系统是微处理器系统。如果微处理器没有访问数据，则在分配的时隙结束时允许转移。如果微处理器正在访问数据，则传输延迟TDM时钟的三个时钟周期。延迟后，如果微处理器仍在访问数据，传输将再次延迟。延迟持续到微处理器不再访问数据，此时允许传输。

189. 发明授权

US4972445A Data transmission apparatus 失效
标题翻译：数据传输装置
公开(公告)号：US4972445A
公开(公告)日：1990-11-20
申请号：US432355
申请日：1989-11-06
申请人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
发明人： Hiroaki Terada , Katsuhiko Asada , Hiroaki Nishikawa , Kenji Shima , Shinji Komori , Souichi Miyata , Satoshi Matsumoto , Hajime Asano , Masahisa Shimizu , Hiroki Miura
IPC分类号： G06F13/42
CPC分类号： G06F13/4217
摘要： A data transmission apparatus for transmitting data between systems includes: an input data transmission path, an output data transmission path, and a branch data transmission path each constituted by a shift register, each data transmission path has a plurality of data storage circuits and a plurality of transfer control circuits each provided corresponding to each o--stage. The data storage circuit control a self stage data storage circuit in accordance with a control signal from the transfer control circuit of an adjacent stage. An initialization circuit for initializing the device is provided so that data on the data transmission path does not remain at the start of operation of the device.
摘要翻译：一种用于在系统之间传输数据的数据传输装置包括：输入数据传输路径，输出数据传输路径和分支数据传输路径，每个移位寄存器由移位寄存器构成，每个数据传输路径都有多个数据存储电路和多个数据传输路径的转移控制电路各自对应于每个o级。数据存储电路根据来自相邻级的传送控制电路的控制信号来控制自身级数据存储电路。提供了一种用于初始化设备的初始化电路，使得数据传输路径上的数据不会保留在设备的操作开始。

190. 发明授权

US4969089A Method of operating a computer system and a multiprocessor system employing such method 失效
标题翻译：操作计算机系统的方法和采用这种方法的多处理器系统
公开(公告)号：US4969089A
公开(公告)日：1990-11-06
申请号：US117015
申请日：1987-11-04
申请人： Hans-Jurgen Jakel
发明人： Hans-Jurgen Jakel
IPC分类号： G06F13/42 , G06F15/16 , G06F15/167
CPC分类号： G06F15/161 , G06F13/4217
摘要： A computer constructed in accordance with the invention includes at least one transmitting and two receiving structural components. At least the receiving structural components are connected with one another by connecting lines that are arranged in parallel with one another. These connecting lines include data lines and also addressing lines by which each of at least the receiving structural components can be uniquely addressed. When addressed by the appropriate addressing signal, the respective receiving structural component reads the data that is then present at the data lines. A decoder is provided in the transmitting structural component. This decoder is operative for decoding the addressing lines which respectively address the receiving structural components in such a manner that simultaneous addressing of several structural components is possible. The receiving structural components are connected with one another and with the transmitting structural component by a common feedback line.
摘要翻译：根据本发明构造的计算机包括至少一个传送和两个接收结构部件。至少接收结构部件通过彼此并联布置的连接线相互连接。这些连接线包括数据线以及至少可以唯一地寻址至少接收结构组件中的每一个的寻址线。当通过适当的寻址信号寻址时，相应的接收结构部件读取随后存在于数据线上的数据。在传输结构部件中提供解码器。该解码器可操作用于解码分别解决接收结构组件的寻址行，使得可以同时寻址多个结构组件。接收结构部件通过公共反馈线彼此连接并且与发射结构部件相连。

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