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161. 发明申请

US20130246872A1 LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS 有权
标题翻译：锁定状态机在STP数据捕获和移动中的运行
公开(公告)号：US20130246872A1
公开(公告)日：2013-09-19
申请号：US13891760
申请日：2013-05-10
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/318555 , G01R31/3177 , G01R31/318572
摘要： A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits.
摘要翻译：在集成电路内选择替代测试电路的过程使得测试访问端口成为可能。扫描测试指令数据被加载到测试访问端口TAP的指令寄存器中，指令数据包括用于选择备用测试电路的信息。在加载结束时执行Update-IR指令更新操作，以从指令寄存器输出扫描测试控制信号。锁定信号变为活动状态以禁用测试访问端口并启用扫描测试电路。

162. 发明申请

US20130232388A1 METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL 有权
公开(公告)号：US20130232388A1
公开(公告)日：2013-09-05
申请号：US13858625
申请日：2013-04-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318544 , G01R31/31855 , G01R31/318555 , G01R31/318575
摘要： Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

163. 发明授权

US08522094B2 Test access and scan test ports with lockout signal terminal 有权
标题翻译：测试访问和扫描测试端口与锁定信号端子
公开(公告)号：US08522094B2
公开(公告)日：2013-08-27
申请号：US13677795
申请日：2012-11-15
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/3172 , G01R31/318536 , G01R31/318555 , G01R31/318572 , G06F1/10
摘要： Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead.
摘要翻译：连接电路将扫描测试端口（STP）电路耦合到测试访问端口（TAP）电路。连接电路具有连接到扫描电路的输入，控制来自TAP电路的输出引线，选择输入引线和时钟输入引线。连接电路具有连接到STP电路的扫描使能（SE）输入引线，捕捉选择（CS）输入引线和扫描时钟（CK）输入引线的输出。连接电路包括多路复用器，其具有与来自TAP电路的时钟选择引线连接的控制输入，与功能时钟引线连接的输入，与时钟输入引线连接的输入，与来自 TAP电路，OFF引线和与扫描时钟输入引线相连的输出。

164. 发明申请

US20130145226A1 BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES 有权
公开(公告)号：US20130145226A1
公开(公告)日：2013-06-06
申请号：US13757334
申请日：2013-02-01
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318536
摘要： An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

165. 发明申请

US20130103996A1 HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS 有权
标题翻译：嵌入式核心集成电路中测试访问端口的分层访问
公开(公告)号：US20130103996A1
公开(公告)日：2013-04-25
申请号：US13712418
申请日：2012-12-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318555 , G01R31/318558 , G01R31/318561 , G01R31/318563 , G01R31/318572
摘要： An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
摘要翻译：集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。这些端口的访问和控制是一个测试链接模块。集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。测试链接模块也可用于仿真。

166. 发明公开

US20240345154A1 INTEGRATED CIRCUIT DIE TEST ARCHITECTURE 审中-公开
公开(公告)号：US20240345154A1
公开(公告)日：2024-10-17
申请号：US18754683
申请日：2024-06-26
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/26 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/2607 , G01R31/3177 , G01R31/318513 , G01R31/318558 , G01R31/318572 , G01R31/318552 , G01R31/318594
摘要： A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

167. 发明公开

US20240337691A1 PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER 审中-公开
公开(公告)号：US20240337691A1
公开(公告)日：2024-10-10
申请号：US18744322
申请日：2024-06-14
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3183 , G01R31/317 , G01R31/3177 , G01R31/3185 , G06F11/273
CPC分类号： G01R31/318335 , G01R31/3172 , G01R31/31723 , G01R31/31727 , G01R31/3177 , G01R31/318547 , G06F11/2733
摘要： The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

168. 发明授权

US12025649B2 Integrated circuit die test architecture 有权
公开(公告)号：US12025649B2
公开(公告)日：2024-07-02
申请号：US18226924
申请日：2023-07-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/26 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/2607 , G01R31/3177 , G01R31/318513 , G01R31/318558 , G01R31/318572 , G01R31/318552 , G01R31/318594
摘要： A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

169. 发明公开

US20240061038A1 AT-SPEED TEST ACCESS PORT OPERATIONS 审中-公开
公开(公告)号：US20240061038A1
公开(公告)日：2024-02-22
申请号：US18386301
申请日：2023-11-02
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/3185 , H10K50/814 , H10K50/816 , H10K50/844 , H10K59/122 , H10K59/123 , H10K59/124 , H10K59/121 , H10K71/00 , G06F11/26 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/318555 , G01R31/318572 , H10K50/814 , H10K50/816 , H10K50/844 , H10K59/122 , H10K59/123 , H10K59/124 , H10K59/1213 , H10K71/00 , G06F11/26 , G01R31/31723 , G01R31/31727 , H10K59/1201
摘要： In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

170. 发明公开

US20240019489A1 SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT 审中-公开
公开(公告)号：US20240019489A1
公开(公告)日：2024-01-18
申请号：US18373447
申请日：2023-09-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/317 , G06F11/27 , G01R31/3185 , G01R31/3177 , G06F11/267
CPC分类号： G01R31/31723 , G06F11/27 , G01R31/31727 , G01R31/318572 , G01R31/3177 , G01R31/31722 , G01R31/31725 , G06F11/267 , G06F11/261
摘要： An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

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