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151. 发明授权

US07310752B2 System and method for on-board timing margin testing of memory modules 有权
标题翻译：内存模块的板载时间裕度测试系统和方法
公开(公告)号：US07310752B2
公开(公告)日：2007-12-18
申请号：US10660844
申请日：2003-09-12
申请人： Joseph M. Jeddeloh
发明人： Joseph M. Jeddeloh
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C29/50012 , G06F11/2221 , G11C5/04 , G11C29/14 , G11C29/48 , G11C29/50 , G11C2029/3602 , G11C2029/5602
摘要： A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.
摘要翻译：存储器模块包括耦合到存储器集线器的若干存储器件。存储器集线器包括耦合到相应处理器的几个链路接口，耦合到相应存储器设备的多个存储器控制器，将任何链接接口耦合到任何存储器控制器的交叉条交换器，每个存储器设备的写入缓冲器和读取高速缓存，以及一个自检模块。自检模块包括产生具有预定图案的写入数据的图形生成器和具有接收写入数据的数据输入的触发器。触发器的时钟输入从接收可变频率时钟发生器的延迟线接收内部时钟信号。与写入数据模式相比，读取数据从存储器件及其模式耦合。可以改变时钟信号的延迟线和频率的延迟以测试存储器件的速度裕度。

152. 发明申请

US20070285986A1 In-circuit Vt distribution bit counter for non-volatile memory devices 有权
标题翻译：用于非易失性存储器件的在线Vt分配位计数器
公开(公告)号：US20070285986A1
公开(公告)日：2007-12-13
申请号：US11448225
申请日：2006-06-07
申请人： Richard K. Eguchi , Larry J. Grieve , Thomas Jew
发明人： Richard K. Eguchi , Larry J. Grieve , Thomas Jew
IPC分类号： G11C11/34
CPC分类号： G11C8/12 , G11C16/04 , G11C29/38 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C29/56008
摘要： Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of 0's or 1's for a specified voltage. As the range of addresses are scanned across a range of voltages, the instances of the count value being counted is accumulated by the bit counter. Automated Tester Equipment (ATE) reads the accumulated count value for each tested voltage.
摘要翻译：非易失性存储器模块中的集成测试组件和测试算法在模块验证过程中提供更快的Vt（阈值电压）分布。存储器模块包括地址和电压扫描组件，以及用于存储指定电压的0或1的数量的位计数器。由于在一定范围的电压范围内扫描地址范围，所以计数的计数值的实例由位计数器累积。自动测试设备（ATE）读取每个测试电压的累计计数值。

153. 发明授权

US07308623B2 Integrated circuit and method for testing memory on the integrated circuit 有权
标题翻译：用于集成电路测试存储器的集成电路和方法
公开(公告)号：US07308623B2
公开(公告)日：2007-12-11
申请号：US11076020
申请日：2005-03-10
申请人： Richard Slobodnik , Paul Stanley Hughes , Frank David Frederick , Brandon Michael Backlund
发明人： Richard Slobodnik , Paul Stanley Hughes , Frank David Frederick , Brandon Michael Backlund
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/26 , G11C29/48 , G11C2029/0401 , G11C2029/3602
摘要： An integrated circuit and method for testing memory on that integrated circuit includes processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided for executing test events in order to seek to detect any memory defects in the number of memory units. The controller includes a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the controller is then operable, following the single programming operation, to execute the sequence of test events.
摘要翻译：用于在该集成电路上测试存储器的集成电路和方法包括可操作以对数据执行数据处理操作的处理逻辑，以及可操作以存储用于由处理逻辑访问的数据的多个存储单元。还提供了用于执行测试事件的存储器测试控制器，以便寻求检测存储器单元数量中的任何存储器缺陷。所述控制器包括存储器，用于存储形成要执行的测试事件序列的多个测试事件中的每一个的事件定义信息，以及在单个编程操作期间接收所述多个测试事件中的每一个的事件定义信息的接口的测试事件，并导致将事件定义为存储在存储器中的信息。然后，控制器中的事件处理逻辑可以在单个编程操作之后执行测试事件的顺序。

154. 发明授权

US07305594B2 Integrated circuit in a maximum input/output configuration 有权
标题翻译：集成电路在最大输入/输出配置
公开(公告)号：US07305594B2
公开(公告)日：2007-12-04
申请号：US10303179
申请日：2002-11-25
申请人： James J. Dietz , David SuitWai Ma
发明人： James J. Dietz , David SuitWai Ma
IPC分类号： G11C29/30 , G11C29/40
CPC分类号： G11C29/1201 , G11C29/48
摘要： A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.
摘要翻译：存储器包括输入/输出路径和电引线。每个输入/输出路径被耦合到单独的电引线。存储器被配置为在测试架构和操作架构中操作。在测试架构中，逻辑允许最大数量的输入/输出路径。在操作架构中，内存使能相同或更少的输入/输出路径。选择配置的方法包括建立操作和测试体系结构，并以更大的输入/输出配置测试存储器。

155. 发明申请

US20070268755A1 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US20070268755A1
公开(公告)日：2007-11-22
申请号：US11436983
申请日：2006-05-19
申请人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
发明人： David New , Paul Darren Hoxey , David Michael Bull , Shidhartha Das
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/12 , G11C29/1201 , G11C29/48 , G11C2207/108
摘要： A memory circuit is provided comprising a memory cell, a pair of conducting lines operable to signal the logic state of the memory cell and read circuitry operable to perform a read operation by detecting a voltage level of at least one of the pair of conducting lines. The memory circuit comprises a pull-down circuit having an on configuration in which it is operable to pull-down a voltage level of at least one of the pair of conducting lines so as to affect the read operation and an off-configuration in which the pull-down circuit cannot affect the read operation. Control circuitry is provided to control whether the pull-down circuit is in the on configuration or the off configuration. The memory circuit can be incorporated in a data processing apparatus and a method of operating a memory circuit is provided in which a pull-down circuit is controlled to be in an on configuration or in an off configuration.
摘要翻译：提供了一种存储器电路，其包括存储单元，一对导线，可操作用于发信号通知存储单元的逻辑状态，读取电路可操作以通过检测至少一对导线的电压来执行读操作。存储器电路包括具有导通配置的下拉电路，其中其可操作以下拉一对导线中的至少一个导线的电压电平，以便影响读取操作，以及关断配置，其中下拉电路不能影响读操作。提供控制电路以控制下拉电路是处于接通配置还是断开配置。存储器电路可以并入数据处理设备中，并且提供了一种操作存储器电路的方法，其中下拉电路被控制为处于接通配置或断开配置。

156. 发明申请

US20070257716A1 Dft Technique for Stressing Self-Timed Semiconductor Memories to Detect Delay Faults 审中-公开
标题翻译：用于强制自定时半导体存储器的Dft技术来检测延迟故障
公开(公告)号：US20070257716A1
公开(公告)日：2007-11-08
申请号：US10591193
申请日：2005-03-03
申请人： Mohamed Azimane , Ananta Majhi
发明人： Mohamed Azimane , Ananta Majhi
IPC分类号： H03L7/00
CPC分类号： G11C29/48 , G11C29/024 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C29/56012
摘要： The present invention relates to a test system (100) interposed between a clock monitor self-timed memory. In an example embodiment, the test system (100) receives an internal clock signal (104) from the clock monitor (152), an external clock signal (CL) and a control signal (CS). A multiplexer (110) of the test system provides in dependence upon the control signal (CS) the internal clock signal (104) to the internal memory block (125) during a normal mode of operation of the self-timed memory and the external clock signal (CL) to the internal memory block (125) during a test mode (108) of the self-timed memory. The test system (100) enables control of the clock cycle of the internal memory block (125) by directly applying the external clock signal (CL) during test mode. Thus, the internal memory block is stressed properly enabling the detection of small delay faults.
摘要翻译：本发明涉及一种插在时钟监视器自定时存储器之间的测试系统（100）。在示例性实施例中，测试系统（100）从时钟监视器（152），外部时钟信号（CL）和控制信号（CS）接收内部时钟信号（104）。在自定时存储器和外部时钟的正常操作模式期间，测试系统的多路复用器（110）根据控制信号（CS）提供内部存储器块（125）的内部时钟信号（104）在自定时存储器的测试模式（108）期间向内部存储器块（125）发送信号（CL）。测试系统（100）通过在测试模式期间直接施加外部时钟信号（CL）来实现内部存储器块（125）的时钟周期的控制。因此，内部存储器块被适当地压缩，能够检测到小的延迟故障。

157. 发明授权

US07278060B2 System and method for on-board diagnostics of memory modules 失效
公开(公告)号：US07278060B2
公开(公告)日：2007-10-02
申请号：US11433130
申请日：2006-05-11
申请人： Joseph M. Jeddeloh
发明人： Joseph M. Jeddeloh
IPC分类号： G06F11/00
CPC分类号： G11C29/56004 , G11C5/04 , G11C29/48 , G11C29/56 , G11C2029/5602
摘要： A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

158. 发明申请

US20070189050A1 Semiconductor chip and semiconductor chip package comprising semiconductor chip 失效
标题翻译：包括半导体芯片的半导体芯片和半导体芯片封装
公开(公告)号：US20070189050A1
公开(公告)日：2007-08-16
申请号：US11702092
申请日：2007-02-05
申请人： Eun-sung Seo , Mi-jo Kim , Soo-young Kim
发明人： Eun-sung Seo , Mi-jo Kim , Soo-young Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/066 , G11C5/04 , G11C8/06 , G11C8/12 , G11C11/40615 , G11C29/1201 , G11C29/48
摘要： Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal generating circuit electrically connected to first and second option pads. In the semiconductor chip, the chip selection signal generating circuit is enabled in accordance with a dual chip enable signal, and the control circuit is enabled and disabled in accordance with the chip selection signal received from the chip selection signal generating circuit. In addition, the chip selection signal generating circuit is adapted to generate a chip selection signal in accordance with signals received through the first and second option pads, respectively.
摘要翻译：本发明的实施例提供一种半导体芯片和包括半导体芯片的半导体芯片封装。在一个实施例中，本发明提供一种半导体芯片，其包括电连接到第一和第二选择焊盘的存储单元阵列，控制电路和芯片选择信号发生电路。在半导体芯片中，芯片选择信号发生电路根据双芯片使能信号使能，并且控制电路根据从芯片选择信号发生电路接收的芯片选择信号而被使能和禁止。此外，芯片选择信号发生电路适于分别根据通过第一和第二可选焊盘接收的信号产生芯片选择信号。

159. 发明授权

US07256594B2 Method and apparatus for testing semiconductor devices using the back side of a circuit board 有权
标题翻译：使用电路板背面测试半导体器件的方法和装置
公开(公告)号：US07256594B2
公开(公告)日：2007-08-14
申请号：US10876346
申请日：2004-06-23
申请人： Chang-Nyun Kim , Sun-Ju Kim , Jong-Hyun Kim , Chung-Koo Yoon , Sang-Jun Park
发明人： Chang-Nyun Kim , Sun-Ju Kim , Jong-Hyun Kim , Chung-Koo Yoon , Sang-Jun Park
IPC分类号： G01R31/02
CPC分类号： G01R31/2886 , G01R1/0408 , G11C29/48 , G11C29/56
摘要： A test system for a semiconductor device couples the device to the back side of a circuit board, thereby allowing the device to be tested under actual operating conditions while providing adequate clearance around the device to accommodate automatic handling equipment, and also reducing signal delay and distortion. A system in accordance with the present invention includes a circuit board having circuitry adapted to provide an actual operating environment for the semiconductor device, as for example, a low cost mother board for testing memory devices. The device is coupled to the back side of the circuit board through test terminals formed on the back side of the board. An interface board can be used to correct the pin arrangements, which are reversed because they protrude from the back side of the board, and to compensate for the environmental differences caused by use of sockets and additional equipment on the interface board.
摘要翻译：用于半导体器件的测试系统将设备耦合到电路板的背面，从而允许在实际操作条件下测试设备，同时在设备周围提供足够的间隙以适应自动处理设备，并且还减少信号延迟和失真。根据本发明的系统包括具有适于为半导体器件提供实际操作环境的电路的电路板，例如用于测试存储器件的低成本母板。该器件通过形成在电路板背面的测试端子耦合到电路板的背面。可以使用接口板来校正引脚布置，这是因为它们从板的背面突出而相反，并且补偿了在接口板上使用插座和附加设备引起的环境差异。

160. 发明授权

US07254071B2 Flash memory devices with trimmed analog voltages 有权
标题翻译：具有微调模拟电压的闪存设备
公开(公告)号：US07254071B2
公开(公告)日：2007-08-07
申请号：US11332567
申请日：2006-01-12
申请人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
发明人： Loc Tu , Jeffrey Lutze , Jun Wan , Jian Chen
IPC分类号： G11C29/00
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C27/005 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/50004 , G11C2029/5004 , G11C2211/5621 , G11C2211/5634
摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
摘要翻译：公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值它提供了选择用于正常操作的最接近的结果。这些DAC取决于我也被修剪的参考源的值。

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