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151. 发明申请

US20110296146A1 HARDWARE INSTRUCTIONS TO ACCELERATE TABLE-DRIVEN MATHEMATICAL FUNCTION EVALUATION 有权
标题翻译：硬件指令以加速表驱动数学函数评估
公开(公告)号：US20110296146A1
公开(公告)日：2011-12-01
申请号：US12788570
申请日：2010-05-27
申请人： Christopher K. Anand , Robert F. Enenkel , Anuroop Sharma , Daniel M. Zabawa
发明人： Christopher K. Anand , Robert F. Enenkel , Anuroop Sharma , Daniel M. Zabawa
IPC分类号： G06F9/302
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/49905 , G06F9/3893
摘要： A set of instructions for implementation in a floating-point unit or other computer processor hardware is disclosed herein. In one embodiment, an extended-range fused multiply-add operation, a first look-up operation, and a second look-up operation are each embodied in hardware instructions configured to be operably executed in a processor. These operations are accompanied by a table which provides a set of defined values in response to various function types, supporting the computation of elementary functions such as reciprocal, square, cube, fourth roots and their reciprocals, exponential, and logarithmic functions. By allowing each of these functions to be computed with a hardware instruction, branching and predicated execution may be reduced or eliminated, while also permitting the use of distributed instructions across a number of execution units.
摘要翻译：本文公开了一组用于在浮点单元或其他计算机处理器硬件中实现的指令。在一个实施例中，扩展范围的融合乘法运算，第一查找操作和第二查找操作各自体现在被配置为在处理器中可操作地执行的硬件指令中。这些操作伴随着一个表，其响应于各种功能类型提供一组定义的值，支持基本函数的计算，例如倒数，平方，立方，第四根及其倒数，指数函数和对数函数。通过允许使用硬件指令来计算这些功能中的每一个，可以减少或消除分支和预测的执行，同时还允许在多个执行单元上使用分布式指令。

152. 发明授权

US08046564B2 Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation 失效
标题翻译：可配置的配对处理元件阵列配置有上下文，由FSM控制器为每个周期生成多周期浮点运算
公开(公告)号：US08046564B2
公开(公告)日：2011-10-25
申请号：US12234507
申请日：2008-09-19
申请人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
发明人： Hoon Mo Yang , Man Hwee Jo , Il Hyun Park , Ki Young Choi
IPC分类号： G06F9/302
CPC分类号： G06F7/483 , G06F7/575 , G06F15/7867 , G06F2207/3896
摘要： Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.
摘要翻译：描述了用于提供形成浮点单元（FPU）处理元件的处理元件（PE）结构的技术，系统和装置。每个处理元件包括从包括另一个PE的一个或多个源接收数据的两个多路复用器（MUX）中的每一个，并从接收到的数据中选择一个值。处理元件包括与两个多路复用器通信的算术逻辑单元（ALU），以从每个多路复用器接收所选择的值作为两个输入值，并且处理所接收的两个输入值以生成ALU的结果。

153. 发明授权

US08024393B2 Processor with improved accuracy for multiply-add operations 有权
标题翻译：处理器具有提高的乘法运算精度
公开(公告)号：US08024393B2
公开(公告)日：2011-09-20
申请号：US11949418
申请日：2007-12-03
申请人： Ying-wai Ho , John L. Kelley , XingYu Jiang
发明人： Ying-wai Ho , John L. Kelley , XingYu Jiang
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the intermediate result from the multiplier unit is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit. By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
摘要翻译：能够执行多加（Madd）操作并结合改进的中间结果处理能力的浮点处理器。浮点处理器包括耦合到加法器单元的乘法器单元。在特定操作模式中，来自乘法器单元的中间结果被处理（即，舍入但不归一化或非规范化）成在加法器单元中更精确和容易管理的表示。通过以这种方式处理中间结果，提高了精度，降低了电路复杂度，可以提高操作速度。

154. 发明授权

US07949696B2 Floating-point number arithmetic circuit for handling immediate values 有权
标题翻译：用于处理立即值的浮点数算术电路
公开(公告)号：US07949696B2
公开(公告)日：2011-05-24
申请号：US11280244
申请日：2005-11-17
申请人： Masaaki Ishii , Koichi Hasegawa , Hiroaki Sakaguchi
发明人： Masaaki Ishii , Koichi Hasegawa , Hiroaki Sakaguchi
IPC分类号： G06F7/00 , G06F7/38 , G06F9/30
CPC分类号： G06F9/30029 , G06F7/483 , G06F9/30014 , G06F9/30025 , G06F9/30167 , G06F2207/3816 , G06F2207/3824
摘要： Disclosed herein is a floating-point number arithmetic circuit for efficiently supplying data to be performed arithmetic operation. The floating-point number arithmetic circuit includes an floating-point number arithmetic unit for performing a predetermined floating-point number arithmetic operation on a floating-point number of a predetermined precision, and a converting circuit for converting data into the floating-point number of predetermined precision and supplying the floating-point number of the predetermined precision to at least either one of input terminals of the floating-point number arithmetic unit.
摘要翻译：这里公开了一种用于有效地提供要进行的算术运算的数据的浮点数运算电路。浮点数算术电路包括用于对预定精度的浮点数执行预定的浮点数算术运算的浮点数运算单元和用于将数据转换为浮点数运算的浮点数运算单元预定精度，并将预定精度的浮点数提供给浮点数运算单元的输入端中的至少一个。

155. 发明授权

US07885992B2 System and method for implementing irregular data formats 失效
标题翻译：用于实现不规则数据格式的系统和方法
公开(公告)号：US07885992B2
公开(公告)日：2011-02-08
申请号：US11759512
申请日：2007-06-07
申请人： Manuel F. Richey , Timothy P. Gibson
发明人： Manuel F. Richey , Timothy P. Gibson
IPC分类号： G06F7/483
CPC分类号： G06F7/49942 , G06F7/483
摘要： A computer system comprises a processing unit configured to process fixed size data words comprising at least one exponent field of variable size and a mantissa of variable size; an input device configured to provide data words to the processing unit; and an output device configured to output data words processed by the processing unit.
摘要翻译：计算机系统包括处理单元，其被配置为处理包括可变大小的至少一个指数字段和可变大小的尾数的固定大小的数据字; 被配置为向所述处理单元提供数据字的输入装置; 以及输出装置，被配置为输出由所述处理单元处理的数据字。

156. 发明申请

US20110010406A1 Programmable Logic Systems and Methods Employing Configurable Floating Point Units 有权
标题翻译：可编程逻辑系统和采用可配置浮点单元的方法
公开(公告)号：US20110010406A1
公开(公告)日：2011-01-13
申请号：US12885103
申请日：2010-09-17
申请人： Hare K. Verma , Ravi Sunkavalli , Manoj Gunwani
发明人： Hare K. Verma , Ravi Sunkavalli , Manoj Gunwani
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/57 , H03K19/17736
摘要： A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.
摘要翻译：公开了一种可编程系统，其具有耦合到多个可编程逻辑和路由块和多个存储器的多个可配置浮点单元（“FPU”）。每个浮点单元具有静态配置块和动态配置块，其中动态配置块可以被重新配置以执行不同的浮点单元功能。浮点单元包括用于移位指数计算以及移位和对准尾数的预归一化，以及用于归一化和舍入所接收的输入的后归一化。后归一化接收输入Z并重新对准输入，对输入进行归一化并舍入输入Z。

157. 发明授权

US07860910B2 System and method for mapping mathematical finite floating-point numbers 有权
标题翻译：用于映射数学有限浮点数的系统和方法
公开(公告)号：US07860910B2
公开(公告)日：2010-12-28
申请号：US11282735
申请日：2005-11-17
申请人： Robert S. Howard
发明人： Robert S. Howard
IPC分类号： G06F15/00
CPC分类号： H03M7/24 , G06F7/026 , G06F7/483 , G06F2207/3832
摘要： A floating-point number is encoded into a binary string. A left-to-right comparison of the binary string determines relative magnitude of the floating-point number. If the floating-point number is negative, then take an absolute value of the floating-point number. The resulting binary string conversion is then complemented. If the floating-point number is zero, then a value for the binary string is assigned. The value is a “1” followed by a plurality of “0”s. A portion of each byte of the binary string determines whether another byte follows in the binary string. A value of a bit of each byte of the binary string determines whether another byte follows. In another aspect, the floating-point number encodes to a binary string having a length as a function of the mantissa and exponent of the floating-point number.
摘要翻译：浮点数被编码成二进制字符串。二进制串的从左到右比较确定浮点数的相对大小。如果浮点数为负，则取绝对值的浮点数。然后对所得到的二进制字符串转换进行补充。如果浮点数为零，则分配二进制字符串的值。该值为“1”，后跟多个“0”。二进制串的每个字节的一部分确定二进制字符串中是否有另一个字节。二进制串的每个字节的位的值确定是否跟随另一个字节。在另一方面，浮点数编码为具有作为浮点数的尾数和指数的函数的长度的二进制串。

158. 发明申请

US20100125621A1 ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF 审中-公开
标题翻译：算术处理装置及其方法
公开(公告)号：US20100125621A1
公开(公告)日：2010-05-20
申请号：US12274996
申请日：2008-11-20
申请人： David S. Oliver , Debjit Das Sarma , Scott Hilker
发明人： David S. Oliver , Debjit Das Sarma , Scott Hilker
IPC分类号： G06F7/52
CPC分类号： G06F7/483 , G06F2207/382
摘要： An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and the second mode supports two simultaneous single-precision computations using the same exponent and mantissa datapaths.
摘要翻译：公开了可以进行乘法运算，加法运算或其组合的运算处理单元。算术处理单元可以在两种模式下操作。第一种模式支持一种单，双精度或扩展精度计算，第二种模式支持使用相同指数和尾数数据路径的两次同时单精度计算。

159. 发明申请

US20100063987A1 SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR 有权
标题翻译：支持浮点处理器中的多个格式
公开(公告)号：US20100063987A1
公开(公告)日：2010-03-11
申请号：US12207067
申请日：2008-09-09
申请人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
发明人： Maarten J. Boersma , K. Michael Kroener , Petra Leber , Silvia M. Mueller , Jochen Preiss , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/483
摘要： In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
摘要翻译：在二进制浮点处理器中，通过使用结果精度（“Emin”）的最小指数值偏移指数，即将重新编码的值转换为内部格式，将各种类型的操作数中的每一个的指数重新编码为内部格式指数是指数减去Emin的表示值。 Emin仅取决于当前正在二进制浮点处理器中执行的指令的结果精度。然后以这种新格式执行指数计算。对所有结果精度的下溢检查是针对零的检查，并且针对取决于结果精度的正数执行溢出检查。指数值为2的补码表示，因此下溢检查简单地成为对符号位的检查。

160. 发明申请

US20090292754A1 METHOD AND SYSTEM FOR AVOIDING UNDERFLOW IN A FLOATING-POINT OPERATION 有权
标题翻译：在浮点操作中避免下流的方法和系统
公开(公告)号：US20090292754A1
公开(公告)日：2009-11-26
申请号：US12533800
申请日：2009-07-31
申请人： Marius A. Cornea-Hasegan
发明人： Marius A. Cornea-Hasegan
IPC分类号： G06F7/38 , G06F7/42
CPC分类号： G06F7/4991 , G06F7/483 , G06F7/5443
摘要： Methods and systems for detecting underflow in a floating-point operation are disclosed. In accordance with an example disclosed method a plurality of comparator circuits and a plurality of logic devices coupled to the plurality of comparator circuits are operated to determine whether performing a floating-point operation using a floating-point hardware unit will generate an underflow condition. The operating of the plurality of comparator circuits and the logic devices involves inputting a multiply-add operation result value to at least some of the plurality of comparator circuits. In addition, a plurality of logic outputs are outputted via the plurality of logic devices. The plurality of logic outputs are indicative of comparison operations performed by at least some of the comparator circuits based on the multiply-add operation result value. An underflow indicator is outputted based on the plurality of logic outputs. The underflow indicator is indicative of whether performing the floating-point operation using the floating-point hardware unit will generate the underflow condition.
摘要翻译：公开了用于检测浮点运算中的下溢的方法和系统。根据公开的示例，操作多个比较器电路和耦合到多个比较器电路的多个逻辑器件，以确定是否使用浮点硬件单元执行浮点运算将产生下溢条件。多个比较器电路和逻辑器件的操作涉及向多个比较器电路中的至少一些比较器电路输入乘法运算结果值。此外，经由多个逻辑器件输出多个逻辑输出。多个逻辑输出表示由至少一些比较器电路基于乘法运算结果值执行的比较运算。基于多个逻辑输出输出下溢指示符。下溢指示器指示使用浮点硬件单元执行浮点运算是否会产生下溢条件。

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