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151. 发明申请

US20050151208A1 Semiconductor switch 有权
标题翻译：半导体开关
公开(公告)号：US20050151208A1
公开(公告)日：2005-07-14
申请号：US11022814
申请日：2004-12-28
申请人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
发明人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
IPC分类号： H01L27/095 , H01L27/12 , H01L29/812 , H01L21/336 , H01L29/94
CPC分类号： H01L27/1203 , H01L29/8126
摘要： In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.
摘要翻译：在本发明的半导体开关中，栅电极，源电极和漏极形成为使得MESFET的栅极和漏极之间的距离（假设分流FET）比栅极和漏极之间的距离长假定通过FET，MESFET的假定为通过FET的MESFET的栅极击穿电压在不改变MESFET的栅极击穿电压的情况下增加，并且假定为通过FET，所以增加了MESFET的栅极击穿电压。

152. 发明申请

US20050139838A1 Semiconductor device and method for manufacturing semiconductor device 审中-公开
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US20050139838A1
公开(公告)日：2005-06-30
申请号：US11019768
申请日：2004-12-23
申请人： Tomohiro Murata , Yutaka Hirose , Tsuyoshi Tanaka , Yasuhiro Uemoto
发明人： Tomohiro Murata , Yutaka Hirose , Tsuyoshi Tanaka , Yasuhiro Uemoto
IPC分类号： H01L21/28 , H01L21/335 , H01L21/338 , H01L29/20 , H01L29/423 , H01L29/778 , H01L29/812 , H01L29/04
CPC分类号： H01L29/66871 , H01L21/28 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L29/8128
摘要： A semiconductor device of the present invention includes: a III-V nitride semiconductor layer including a channel region in which carriers travel; a concave portion provided in an upper portion of the channel region in the III-V nitride semiconductor layer; and a Schottky electrode consisting of a conductive material forming a Schottky junction with the semiconductor layer, and formed on a semiconductor layer, which spreads over the concave portion and peripheral portions of the concave portion, on the III-V nitride semiconductor layer. A dimension of the concave portion in a depth direction is set so that a portion of the Schottky electrode provided in the concave portion can adjust a quantity of the carriers traveling in the channel region.
摘要翻译：本发明的半导体器件包括：III-V族氮化物半导体层，其包括载流子行进的沟道区; 设置在III-V族氮化物半导体层中的沟道区的上部的凹部; 和由形成与半导体层形成肖特基结的导电材料构成的肖特基电极，形成在III-V族氮化物半导体层上的在凹部的凹部和周边部分上方扩散的半导体层上。深度方向上的凹部的尺寸被设定为使得设置在凹部中的肖特基电极的一部分可以调节在沟道区域中行进的载流子的量。

153. 发明申请

US20050121696A1 Semiconductor device and hetero-junction bipolar transistor 有权
标题翻译：半导体器件和异质结双极晶体管
公开(公告)号：US20050121696A1
公开(公告)日：2005-06-09
申请号：US10927525
申请日：2004-08-27
申请人： Satoshi Nakazawa , Yutaka Hirose , Tsuyoshi Tanaka
发明人： Satoshi Nakazawa , Yutaka Hirose , Tsuyoshi Tanaka
IPC分类号： H01L21/331 , H01L29/20 , H01L29/737 , H01L29/739
CPC分类号： H01L29/66318 , H01L29/2003 , H01L29/7371
摘要： In an npn-type HBT, each of an emitter layer and a collector layer is formed of AlGaN and a base layer is formed of GaN. The emitter layer is in contact with a nitrogen polarity surface of the base layer and the collector layer is in contact with a gallium polarity surface of the base layer. An electric charge is generated at each interface due to a spontaneous polarization and a piezo polarization generated in each of the layers. Because of the electric charge, an internal field is generated so as to accelerate electrons in the base layer.
摘要翻译：在npn型HBT中，发射极层和集电极层由AlGaN构成，基底层由GaN形成。发射极层与基极层的氮极性表面接触，并且集电极层与基极层的镓极性表面接触。由于在各层中产生的自发极化和压电极化，在每个界面产生电荷。由于电荷，产生内部场以加速基底层中的电子。

154. 发明申请

US20050068059A1 Suppressing the leakage current in an integrated circuit 审中-公开
标题翻译：抑制集成电路中的漏电流
公开(公告)号：US20050068059A1
公开(公告)日：2005-03-31
申请号：US10962893
申请日：2004-10-12
申请人： Hiroshi Takahashi , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Tsuyoshi Tanaka , Rimon Ikeno
发明人： Hiroshi Takahashi , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Tsuyoshi Tanaka , Rimon Ikeno
IPC分类号： H01L21/822 , G11C5/14 , H01L27/04 , H01L31/0336 , H03K17/687 , H03K19/00 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00315 , G11C5/14 , H03K19/0016
摘要： A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage Vdd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage VB equal to or higher than source voltage Vdd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.
摘要翻译：一种半导体集成电路，其中电路面积可以最小化，并且在待机状态期间可以可靠地检测缺陷，同时保持栅氧化膜的可靠性。开关电路20设置在逻辑电路10和源电压Vdd供电端子之间。在工作状态下，将0V电压施加到开关电路20的晶体管MP0的栅极，并将等于或略低于源极电压Vdd的偏置电压VB施加到其沟道区，以便降低晶体管的阈值电压 MP0并提高其目前的驾驶能力。在待机状态下，将等于源极电压Vdd的电压施加到晶体管MP0的栅极，将低于源极电压的电压施加到源极，施加等于或高于源极电压Vdd的体偏置电压Vdd 到沟道区域，以使晶体管MP0的漏极电流最小化，使得逻辑电路10的电流路径被切断，并且抑制了泄漏电流的发生。

155. 发明授权

US06852580B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06852580B2
公开(公告)日：2005-02-08
申请号：US10150326
申请日：2002-05-20
申请人： Manabu Yanagihara , Tsuyoshi Tanaka , Akihisa Sugimura
发明人： Manabu Yanagihara , Tsuyoshi Tanaka , Akihisa Sugimura
IPC分类号： H01L21/328 , G05F3/20 , H03F1/30 , H01L21/338
CPC分类号： H03F1/302 , G05F3/205
摘要： The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.
摘要翻译：本发明提供一种用于抑制功率晶体管的空载电流随温度变化的偏置电路和包括该偏置电路的半导体器件。偏置电路包括具有发射极，基极和集电极的第一双极晶体管和连接到第一双极晶体管的基极的至少一个肖特基二极管，并且提供至少一个肖特基二极管以提供用于抑制的基极电位第一双极晶体管的集电极电流根据温度变化而变化。

156. 发明授权

US06850103B2 Low leakage single-step latch circuit 有权
标题翻译：低泄漏单步锁存电路
公开(公告)号：US06850103B2
公开(公告)日：2005-02-01
申请号：US10259128
申请日：2002-09-27
申请人： Rimon Ikeno , Kaoru Awaka , Tsuyoshi Tanaka , Hiroshi Takahashi , Yutaka Toyonoh , Akihiro Takegama
发明人： Rimon Ikeno , Kaoru Awaka , Tsuyoshi Tanaka , Hiroshi Takahashi , Yutaka Toyonoh , Akihiro Takegama
IPC分类号： H03K3/012 , H03K3/037 , H03K3/289 , H03K3/356
CPC分类号： H03K3/0375 , H03K3/012
摘要： This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch transistors. The techniques require changes only in the circuit configuration. Neither higher cost technology such as multiple-threshold LVT/HVT transistors nor special control circuits are needed.
摘要翻译：本发明描述了提供用于在具有开关晶体管的单步锁存器中实现可靠数据保持和低泄漏电流的装置的电路技术。这些技术只需要在电路配置中进行更改。既不需要诸如多阈值LVT / HVT晶体管的高成本技术，也不需要特殊的控制电路。

157. 发明授权

US06828752B2 Driving equipment and semiconductor equipment for alternating-current motor 失效
标题翻译：用于交流电动机的驱动设备和半导体设备
公开(公告)号：US06828752B2
公开(公告)日：2004-12-07
申请号：US10606960
申请日：2003-06-27
申请人： Junnosuke Nakatsugawa , Hitoshi Ohura , Tsuyoshi Tanaka , Tunehiro Endo , Yukio Kawabata
发明人： Junnosuke Nakatsugawa , Hitoshi Ohura , Tsuyoshi Tanaka , Tunehiro Endo , Yukio Kawabata
IPC分类号： H02P534
CPC分类号： H02P6/10 , H02P29/50 , H02P2209/07
摘要： The present invention enables modulated wave signals having extremely small waveform distortion to be generated using a relatively simple circuit, and thereby it is possible to hold down vibrations and noise of a motor, which are attributable to torque ripples. In order to remove defects of the conventional techniques, the circuit generates a plurality of trapezoidal wave signals having at least two constant levels based on position sensing signals of magnetic pole of a motor, generates quasi-sinusoidal wave signals at a quasi-sinusoidal wave modulator based on the plurality of trapezoidal wave signals, and compares the quasi-sinusoidal wave signals with a carrier wave so as to perform PWM control of an inverter.
摘要翻译：本发明使得能够使用相对简单的电路产生具有极小波形失真的调制波信号，从而可以抑制归因于转矩波动的电动机的振动和噪声。为了消除常规技术的缺陷，电路基于电机的磁极的位置感测信号产生具有至少两个恒定电平的多个梯形波信号，在准正弦波调制器处产生准正弦波信号基于多个梯形波信号，并且将准正弦波信号与载波进行比较，以便执行逆变器的PWM控制。

158. 发明授权

US06798734B1 Optical recording medium having address pits in the header region connecting with each other 失效
标题翻译：具有彼此连接的头部区域中的地址坑的光学记录介质
公开(公告)号：US06798734B1
公开(公告)日：2004-09-28
申请号：US09787811
申请日：2001-07-03
申请人： Tatsuo Kawasaki , Koyata Takahashi , Kenichi Sekimoto , Toru Futami , Shigeru Hiramatsu , Mutsumi Asano , Yuji Kawara , Tsuyoshi Tanaka
发明人： Tatsuo Kawasaki , Koyata Takahashi , Kenichi Sekimoto , Toru Futami , Shigeru Hiramatsu , Mutsumi Asano , Yuji Kawara , Tsuyoshi Tanaka
IPC分类号： G11B724
CPC分类号： G11B7/24085 , G11B7/00718 , G11B7/00745 , G11B7/08505
摘要： An optical recording medium able to reproduce address information during seeking in which an optical head moves between tracks, to increase seek speed, to improve recording/reproduction speed and to obtain a good header reproducing signal is achieved by that the concave portions or convex portions constituting a reproducing signal in seeking reproduced even during seek and/or constituting a timing signal for writing a header signal are connected to each other in a direction orthogonal to the tracks, when these concave portions and/or convex portions are placed in positions equivalent to each other in the adjacent tracks.
摘要翻译：一种光学记录介质，其能够在光头在轨道之间移动的寻道期间再现地址信息，从而提高寻道速度，提高记录/再现速度并获得良好的标题再现信号，通过构成即使在搜索期间再寻求再现信号和/或构成用于写入标题信号的定时信号的再现信号在与轨道正交的方向上彼此连接，当这些凹部和/或凸部位于相当于每个其他在相邻的轨道。

159. 发明授权

US06779148B2 Error detection and correction method in a computer system and main memory controller of the same 失效
标题翻译：计算机系统和主存储器控制器中的错误检测和校正方法
公开(公告)号：US06779148B2
公开(公告)日：2004-08-17
申请号：US09805169
申请日：2001-03-14
申请人： Tsuyoshi Tanaka
发明人： Tsuyoshi Tanaka
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H03M13/15
摘要： According to an error detection and correction method to be implemented in a computer system, when an error is detected in data to be written in a memory, fault information is appended to the data without an increase in the number of bits constituting the data, and the resultant data is stored in the memory. An error control code represented by a SEC-DEC code is adopted for encoding and decoding. Data is encoded into a shortened code. At this time, specific bit positions associated with column vectors deleted from a parity check matrix defined in the error control code are allocated to fault information. Thus, a word to be actually stored in the memory is composed of check bits produced from data to be written and fault information, and information bits constituting the data to be written. Decoding is performed on the assumption that the fault information represents 0s. When data having fault information appended thereto is decoded, the fault information is reproduced through error detection and correction.
摘要翻译：根据要在计算机系统中实现的错误检测和校正方法，当在要写入存储器的数据中检测到错误时，将错误信息附加到数据，而不增加构成数据的位数，并且结果数据被存储在存储器中。采用由SEC-DEC代码表示的错误控制码用于编码和解码。数据被编码成缩短的代码。此时，将从错误控制代码中定义的奇偶校验矩阵中删除的列向量相关联的特定位位置分配给故障信息。因此，实际存储在存储器中的字由由要写入的数据和故障信息产生的校验位和构成要写入的数据的信息位组成。假设故障信息表示0s，进行解码。当附加有故障信息的数据被解码时，通过错误检测和校正再现故障信息。

160. 发明授权

US06263405B1 Multiprocessor system 失效
标题翻译：多处理器系统
公开(公告)号：US06263405B1
公开(公告)日：2001-07-17
申请号：US09134336
申请日：1998-08-14
申请人： Naohiko Irie , Naoki Hamanaka , Tsuyoshi Tanaka , Masabumi Shibata , Atsushi Nakajima
发明人： Naohiko Irie , Naoki Hamanaka , Tsuyoshi Tanaka , Masabumi Shibata , Atsushi Nakajima
IPC分类号： G06F1212
CPC分类号： G06F12/0815 , G06F12/0813
摘要： A cache status report sum up for use in a multiprocessor system having a plurality of processor units each having a processor and a cache memory and a plurality of memory units. The cache status report sum up apparatus sums up cache coherency check results indicating statuses of the cache memories without limiting the number of memory access requests requiring cache coherency checks that can be overlapped when the memory access requests requiring cache coherency checks are executed in an overlapping manner. The cache status report sum up apparatus is provided between the processor units and the memory units and sums up cache coherency check results sent by cache status reporting apparatus included in each processor unit. The cache status reporting apparatus responds to a memory access request requiring a cache coherency check. The cache status report sum up apparatus, after summing up the cache coherency check results, sends the summary of the cache coherency check results to the processor unit which requested the memory access request requiring a cache coherency check.
摘要翻译：高速缓存状态报告总结为在具有多个处理器单元的多处理器系统中使用，每个处理器单元各自具有处理器和高速缓冲存储器以及多个存储器单元。高速缓存状态报告总结装置总结高速缓存一致性检查结果，指示高速缓存存储器的状态，而不限制需要高速缓存一致性检查的存储器访问请求的数量，当需要高速缓存一致性检查的存储器访问请求以重叠的方式执行时可重叠。在处理器单元和存储器单元之间提供高速缓存状态报告总结装置，并且对由每个处理器单元中包括的高速缓存状态报告装置发送的高速缓存一致性检查结果求和。高速缓存状态报告装置响应需要高速缓存一致性检查的存储器访问请求。高速缓存状态报告总结装置在总结高速缓存一致性检查结果之后，将高速缓存一致性检查结果的摘要发送到请求需要高速缓存一致性检查的存储器访问请求的处理器单元。

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