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141. 发明申请

US20120238110A1 HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH FLASH OF LIGHT 有权
标题翻译：热处理方法和热处理装置通过用闪光灯照射基板来加热基板
公开(公告)号：US20120238110A1
公开(公告)日：2012-09-20
申请号：US13366414
申请日：2012-02-06
申请人： Kenichi YOKOUCHI
发明人： Kenichi YOKOUCHI
IPC分类号： H01L21/263 , F27D11/00
CPC分类号： H01L21/324 , F27B17/0025 , H01L21/67115 , H01L21/67748 , H01L21/68742 , H01L21/68785
摘要： The first flash irradiation is performed on a semiconductor wafer preheated to 500° C. to heat a front surface of the semiconductor wafer. Thereafter, the second flash irradiation is performed to reheat the front surface of the semiconductor wafer before the temperature of the front surface of the semiconductor wafer becomes equal to the temperature of a back surface of the semiconductor wafer. Thus, the second flash irradiation is performed before the temperature of the front surface of the semiconductor wafer falls. Even if less energy is consumable by the second flash irradiation, the efficiency of heating of the front surface of the semiconductor wafer resulting from each iteration of the flash irradiation is improved.
摘要翻译：在预热到500℃的半导体晶片上进行第一闪光照射，以加热半导体晶片的前表面。此后，在半导体晶片的正面的温度变得等于半导体晶片的背面的温度之前，进行第二闪光照射，以对半导体晶片的前表面再加热。因此，在半导体晶片的正面的温度下降之前进行第二闪光照射。即使通过第二闪光照射消耗较少的能量，由于闪光照射的每次迭代而导致的半导体晶片的正面的加热效率提高。

142. 发明申请

US20120214319A1 METHOD OF IMPROVING THE PASSIVATION EFFECT OF FILMS ON A SUBSTRATE 审中-公开
标题翻译：改善薄膜对基底的钝化效应的方法
公开(公告)号：US20120214319A1
公开(公告)日：2012-08-23
申请号：US13396286
申请日：2012-02-14
申请人： Yuanchang Zhang
发明人： Yuanchang Zhang
IPC分类号： H01L21/263
CPC分类号： H01L31/1868 , Y02E10/50 , Y02P70/521
摘要： A film deposited on substrate may originally has a high surface recombination velocity (SRV). In order to suppress the SRV and increase the minority carrier lifetime, the substrate may be treated annealing at a high temperature in gas ambient containing O2 or O2−. The substrate may also be treated annealing at a low or mild temperature in gas ambient containing H2 or H+. The process has been found to improve the passivation effect of silicon oxide thin films on a silicon substrate. Further, the process can be achieved using the same production steps normally applied to the solar cell to create its top and bottom metal contacts without additional heating cycles are required.
摘要翻译：沉积在基底上的薄膜最初可具有高的表面复合速度（SRV）。为了抑制SRV并增加少数载流子寿命，可以在含有O 2或O 2 - 的气体环境中在高温下对衬底进行处理退火。衬底也可以在含有H 2或H +的气体环境中在低温或温和的温度下进行退火处理。已经发现该方法可以改善硅衬底上氧化硅薄膜的钝化效果。此外，该方法可以使用通常应用于太阳能电池的相同生产步骤来实现，以产生其顶部和底部金属触点，而不需要额外的加热循环。

143. 发明申请

US20120214314A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US20120214314A1
公开(公告)日：2012-08-23
申请号：US13401537
申请日：2012-02-21
申请人： Thomas SCHARNAGL , Berthold STAUFER
发明人： Thomas SCHARNAGL , Berthold STAUFER
IPC分类号： H01L21/263
CPC分类号： H01L29/66272 , H01L21/8228 , H01L27/082
摘要： A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other
摘要翻译：一种用于制造包括互补双极晶体管的半导体结构的方法，其中为了制造PNP型结构，具有表面氧化物层的发射极层位于NPN型结构的顶部，发射极层包括横向和垂直表面，并且其中为了去除氧化物层，应用离子蚀刻步骤，其中对于上蚀刻步骤，通过RF耦合在真空室中产生用于提供离子的等离子体，并且所产生的离子通过等离子体和包括半导体结构的晶片，并且其中等离子体产生和离子加速彼此独立地被控制

144. 发明授权

US08216919B2 Method of manufacturing a semiconductor device and substrate carrier structure 有权
标题翻译：制造半导体器件和衬底载体结构的方法
公开(公告)号：US08216919B2
公开(公告)日：2012-07-10
申请号：US13009673
申请日：2011-01-19
申请人： Yuichi Kaneko
发明人： Yuichi Kaneko
IPC分类号： H01L21/263
CPC分类号： H01L21/6835 , H01L2221/68313 , H01L2221/6835
摘要： A substrate carrier structure includes a tray and a secondary electron absorbing material. The tray holds a semiconductor substrate having a first surface on which semiconductor device elements are formed. The secondary electron absorbing material is interposed between the tray and this first surface of the semiconductor substrate. When the semiconductor substrate is irradiated with charged particles to form lattice defects, the secondary electron absorbing material prevents unwanted trapping of secondary electrons emitted from the tray, and thereby reduces the variability of electrical characteristics of semiconductor device elements formed on the semiconductor substrate.
摘要翻译：衬底载体结构包括托盘和二次电子吸收材料。托盘保持具有形成半导体器件元件的第一表面的半导体衬底。二次电子吸收材料介于托盘和半导体衬底的第一表面之间。当半导体衬底被带电粒子照射以形成晶格缺陷时，二次电子吸收材料防止从托盘发射的二次电子的不期望的捕获，从而减少形成在半导体衬底上的半导体器件元件的电特性的变化。

145. 发明申请

US20110318919A1 SURFACE TREATMENT FOR A FLUOROCARBON FILM 有权
标题翻译：荧光膜的表面处理
公开(公告)号：US20110318919A1
公开(公告)日：2011-12-29
申请号：US13138242
申请日：2010-01-22
申请人： Masahiro Horigome , Takuya Kurotori , Yasuo Kobayashi , Takaaki Matsuoka , Toshihisa Nozawa
发明人： Masahiro Horigome , Takuya Kurotori , Yasuo Kobayashi , Takaaki Matsuoka , Toshihisa Nozawa
IPC分类号： H01L21/768 , H01L21/263
CPC分类号： H01L21/32051 , H01L21/02115 , H01L21/02274 , H01L21/2855 , H01L21/3105 , H01L21/3146 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/76864
摘要： A method for manufacturing semiconductor devices includes the steps of annealing an insulating layer and forming a barrier layer including a metal element over the insulating layer. The insulating layer includes a fluorocarbon (CFx) film. The barrier layer is formed by a high-temperature sputtering process after the annealing step.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在绝缘层上退火绝缘层并形成包含金属元件的阻挡层。绝缘层包括碳氟化合物（CFx）膜。在退火步骤之后通过高温溅射工艺形成阻挡层。

146. 发明申请

US20110253977A1 NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：基于氮化物的半导体器件及其制造方法
公开(公告)号：US20110253977A1
公开(公告)日：2011-10-20
申请号：US13167064
申请日：2011-06-23
申请人： Mitsuaki OYA , Toshiya YOKOGAWA , Atsushi YAMADA , Akihiro ISOZAKI
发明人： Mitsuaki OYA , Toshiya YOKOGAWA , Atsushi YAMADA , Akihiro ISOZAKI
IPC分类号： H01L33/06 , H01L29/201 , H01L21/263
CPC分类号： H01L21/28575 , H01L33/16 , H01L33/32 , H01L33/40
摘要： A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes a Zn layer 32 and an Ag layer 34 provided on the Zn layer 32. The Zn layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.
摘要翻译：氮化物系半导体发光装置100具备：具有m面面12的GaN衬底10; 设置在GaN衬底10的m面表面12上的半导体多层结构20; 以及设置在半导体多层结构体20上的电极30.电极30包括Zn层32和设置在Zn层32上的Ag层34.Zn层32与p型半导体区域的表面接触半导体多层结构20。

147. 发明授权

US07998846B2 3-D integrated circuit system and method 有权
标题翻译： 3-D集成电路系统及方法
公开(公告)号：US07998846B2
公开(公告)日：2011-08-16
申请号：US12209478
申请日：2008-09-12
申请人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
发明人： Eunha Kim , Jeremy Wahl , Shenqing Fang , YouSeok Suh , Kuo-Tung Chang , Yi Ma , Rinji Sugino , Jean Yang
IPC分类号： H01L21/263
CPC分类号： H01L21/02675 , H01L21/02592 , H01L21/02691
摘要： A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.
摘要翻译：提出了半导体制造系统和方法。三维多层集成电路制造方法可以包括通过利用受控激光层形成退火工艺形成第一器件层并在第一器件层顶部形成第二器件层，并以最小的有害热传递到第一层。可以利用受控激光结晶过程，并且受控激光器可以包括产生非晶层; 限定非晶层中的结晶区域，其中结晶区域被限定为促进单晶生长（即防止多晶生长）; 以及将激光施加到结晶区域，其中以防止不希望的热传递到另一层的方式施加激光。

148. 发明申请

US20110115027A1 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS 有权
标题翻译：结构和方法来获取电子尺寸的电介质堆叠
公开(公告)号：US20110115027A1
公开(公告)日：2011-05-19
申请号：US12620234
申请日：2009-11-17
申请人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
发明人： Hemanth Jagannathan , Takashi Ando , Lisa F. Edge , Sufi Zafar , Changhwan Choi , Paul C. Jamison , Vamsi K. Paruchuri , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/263
CPC分类号： H01L29/42364 , H01L21/225 , H01L21/28088 , H01L21/28176 , H01L21/28185 , H01L21/324 , H01L21/477 , H01L21/823462 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/401 , H01L29/4958 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/517
摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.
摘要翻译：提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠材料掺杂元素。在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

149. 发明授权

US07888585B2 Photovoltaic module including tap cells and method of making 失效
标题翻译：光伏组件包括龙头电池和制造方法
公开(公告)号：US07888585B2
公开(公告)日：2011-02-15
申请号：US11998156
申请日：2007-11-28
申请人： Peter Lechner , Walter Psyk , Erwin Heckel
发明人： Peter Lechner , Walter Psyk , Erwin Heckel
IPC分类号： H01L31/0224 , H01L31/05 , H01L21/263 , H01L21/28
CPC分类号： H01L31/0201 , H01L31/046 , H01L31/0475 , H02S40/36 , Y02E10/50
摘要： A photovoltaic module includes a plurality of interconnected submodules. Each submodule has a transparent front electrode layer, a semiconductor layer and a back electrode layer which have separating lines in each case for forming series-connected strip-shaped photovoltaic cells. The outer cells of two adjacent submodules are united into a single tap cell for current collection, the separating lines of the two adjacent submodules being disposed mirror-symmetrically with respect to their common tap cell.
摘要翻译：光伏模块包括多个互连的子模块。每个子模块具有透明的前电极层，半导体层和背电极层，其在每种情况下具有用于形成串联连接的带状光伏电池的分离线。将两个相邻的子模块的外部单元组合成单个抽头单元用于电流采集，两个相邻子模块的分离线相对于它们的共同抽头单元镜像对称地布置。

150. 发明申请

US20100317140A1 TECHNIQUES FOR FORMING THIN FILMS BY IMPLANTATION WITH REDUCED CHANNELING 有权
标题翻译：通过减少通道进行植入形成薄膜的技术
公开(公告)号：US20100317140A1
公开(公告)日：2010-12-16
申请号：US12778989
申请日：2010-05-12
申请人： ADAM BRAILOVE , Zuqin Liu , Francois J. Henley , Albert J. Lamm
发明人： ADAM BRAILOVE , Zuqin Liu , Francois J. Henley , Albert J. Lamm
IPC分类号： H01L21/263 , H01J37/08
CPC分类号： H01L31/0392 , H01L21/67213 , H01L21/76254 , H01L31/18 , Y02E10/50
摘要： Embodiments of the present invention relate to the use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate having a top surface is exposed to a beam of accelerated particles. Then, a thin film of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. To improve uniformity of depth of implantation, channeling effects are reduced by one or more techniques. In one technique, a miscut bulk substrate is subjected to the implantation, such that the lattice of the substrate is offset at an angle relative to the impinging particle beam. According to another technique, the substrate is tilted at an angle relative to the impinging particle beam. In still another technique, the substrate is subjected to a dithering motion during the implantation. These techniques may be employed alone or in combination.
摘要翻译：本发明的实施例涉及使用粒子加速器束从大量衬底形成材料薄膜。在具体的实施方案中，具有顶表面的本体衬底暴露于加速颗粒束。然后，通过沿着从光束注入的颗粒形成的切割区域进行受控的切割过程，将薄膜材料与本体基板分离。为了改善植入深度的均匀性，可以通过一种或多种技术降低沟道效应。在一种技术中，对杂散块体基板进行注入，使得基板的晶格相对于撞击的粒子束以一定角度偏移。根据另一种技术，衬底相对于撞击粒子束以一定角度倾斜。在另一种技术中，衬底在植入期间经历抖动运动。这些技术可以单独使用或组合使用。

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