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141. 发明申请

US20070075356A1 Strained silicon device 有权
标题翻译：应变硅器件
公开(公告)号：US20070075356A1
公开(公告)日：2007-04-05
申请号：US11549002
申请日：2006-10-12
申请人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Cheng-Chuan Huang , Fu-Liang Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/7842 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7843 , H01L29/78621
摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.
摘要翻译：微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

142. 发明授权

US07161204B2 DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
标题翻译： DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积
公开(公告)号：US07161204B2
公开(公告)日：2007-01-09
申请号：US11098112
申请日：2005-04-04
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

143. 发明申请

US20060157791A1 ESD protection device 审中-公开
标题翻译： ESD保护装置
公开(公告)号：US20060157791A1
公开(公告)日：2006-07-20
申请号：US11037868
申请日：2005-01-18
申请人： Jian-Hsing Lee , Fu-Liang Yang , Chien-Chao Huang
发明人： Jian-Hsing Lee , Fu-Liang Yang , Chien-Chao Huang
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection device. A first-type well is formed on an insulating layer. First and second second-type doped regions are formed on the first-type well. A first body-tie region is formed on the first-type well and is connected to one side of the first and the second second-type doped regions. A polysilicon gate layer is formed on the first-type well and the body-tie region, and is located between the first and the second second-type doped regions. The first first-type doped region is connected to the first body-tie region. The second first-type doped region is formed on the first-type well.
摘要翻译： ESD保护装置。在绝缘层上形成第一型阱。第一和第二二次掺杂区形成在第一型阱上。在第一类型阱上形成第一结扎区，并连接到第一和第二第二类型掺杂区的一侧。多晶硅栅层形成在第一型阱和体结区上，位于第一和第二第二掺杂区之间。第一第一掺杂区域连接到第一贴合区域。在第一型阱上形成第二第一掺杂区。

144. 发明授权

US06974730B2 Method for fabricating a recessed channel field effect transistor (FET) device 失效
标题翻译：凹陷通道场效应晶体管（FET）器件的制造方法
公开(公告)号：US06974730B2
公开(公告)日：2005-12-13
申请号：US10739476
申请日：2003-12-17
申请人： Carlos H. Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
发明人： Carlos H. Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/66545 , H01L29/66621 , H01L29/78621 , H01L29/78654
摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
摘要翻译：用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。根据上述特征，以增强的性能制造场效应晶体管器件。

145. 发明申请

US20050023569A1 Field effect transistor (FET) device having corrugated structure and method for fabrication thereof 有权
标题翻译：具有波纹状结构的场效应晶体管（FET）器件及其制造方法
公开(公告)号：US20050023569A1
公开(公告)日：2005-02-03
申请号：US10632379
申请日：2003-08-01
申请人： Fu-Liang Yang
发明人： Fu-Liang Yang
IPC分类号： H01L29/10 , H01L29/76 , H01L29/78
CPC分类号： H01L29/78 , H01L29/1037
摘要： Within both a field effect transistor (FET) device and a method for fabricating the field effect transistor (FET) device there is provided: (1) a semiconductor substrate; (2) a gate electrode formed over the semiconductor substrate and covering a channel region within the semiconductor substrate; and (3) a pair of source/drain regions formed within the semiconductor substrate and separated by the channel region within the semiconductor substrate. Within both the field effect transistor (FET) device and the method for fabricating the field effect transistor (FET) device, at least one of: (1) an interface of the channel region covered by the gate electrode; and (2) an upper surface of the gate electrode, is corrugated.
摘要翻译：在场效应晶体管（FET）器件和制造场效应晶体管（FET）器件的方法中，提供：（1）半导体衬底; （2）形成在所述半导体衬底上并覆盖所述半导体衬底内的沟道区的栅电极; 和（3）形成在半导体衬底内并由半导体衬底内的沟道区隔开的一对源/漏区。在场效应晶体管（FET）器件和制造场效应晶体管（FET）器件的方法中，至少一个：（1）由栅电极覆盖的沟道区的界面; 和（2）栅电极的上表面是波纹状的。

146. 发明授权

US06248643B1 Method of fabricating a self-aligned contact 有权
标题翻译：制造自对准接触的方法
公开(公告)号：US06248643B1
公开(公告)日：2001-06-19
申请号：US09285534
申请日：1999-04-02
申请人： Chien-Sheng Hsieh , Wei-Ray Lin , Fu-Liang Yang , Erik S. Jeng , Bor-Ru Sheu
发明人： Chien-Sheng Hsieh , Wei-Ray Lin , Fu-Liang Yang , Erik S. Jeng , Bor-Ru Sheu
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/32053 , H01L21/76224 , H01L21/76879 , H01L21/76885
摘要： A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, a dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.
摘要翻译：一种使用升高的沟槽隔离，选择性接触插塞沉积和平面化从器件级开始制造自对准触点的方法。该工艺开始于在硅衬底上依次形成栅氧化层和第一栅电极层。接下来，使用牺牲氧化物和氮化物层和选择性蚀刻形成完全平坦化的沟槽隔离区域。形成牺牲衬垫氧化物层和第一牺牲氮化物层。图案化第一牺牲氮化物层，牺牲焊盘氧化物层，第一栅极电极层，栅极氧化物层和硅衬底以形成沟槽。填充氧化物层沉积在沟槽中并在第一牺牲氮化物层上方。执行氧化物蚀刻，其将沟槽中的填充氧化物层的凹陷低于第一氮化物层的顶部的水平面。第二牺牲氮化物层形成在填充氧化物层上并在第一牺牲氮化物层上方。进行化学机械抛光。执行连续氧化物蚀刻，氮化物蚀刻和氧化物蚀刻步骤，定义与第一栅极电极层完全平坦化的升高的沟槽隔离区域。形成硅化物层，电介质层和顶部氮化物层。在顶部氮化物层，电介质层，硅化物层，第一栅极电极层和栅极氧化物层之间，在升高的沟槽隔离区域和升高的沟槽隔离区域上的导电线之间构图形成栅极结构。隔板形成在栅极结构，导电线和升高的沟槽隔离区的侧壁上。然后，在间隔物附近形成自对准的接触塞。

147. 发明授权

US06239034B1 Method of manufacturing inter-metal dielectric layers for semiconductor devices 有权
标题翻译：制造用于半导体器件的金属间介电层的方法
公开(公告)号：US06239034B1
公开(公告)日：2001-05-29
申请号：US09184344
申请日：1998-11-02
申请人： Fu-Liang Yang , Liang-Tung Chang
发明人： Fu-Liang Yang , Liang-Tung Chang
IPC分类号： H01L21311
CPC分类号： H01L21/316 , H01L21/31051 , H01L21/31612 , H01L21/76801 , H01L21/76837
摘要： A method of manufacturing an inter-metal level dielectric layer for a semiconductor device. The method includes forming spaced conductive lines. Next, a first conformal silicon oxide film (barrier layer) is formed over the spaced conductive lines. Gaps or valleys are between the metal lines covered by the barrier layer. A novel first “gap filling” spin-on-glass layer is formed over the first silicon oxide layer. In a critical step, the first SOG layer is heated to reflow thereby flowing all the first spin-on-glass layer from over the metal lines and leaving all of the first SOG layer in the gaps. Subsequently, a second silicon oxide layer is deposited over the first silicon oxide layer and over the first spin-on-glass layer only in the gaps. A second spin-on-glass layer is then formed over the second silicon oxide layer. An etchback is performed by etching back and removing the entire second spin on glass layer and portions the second silicon oxide layer. Lastly, an insulating cap layer of silicon oxide or silicon nitride is formed over the second silicon oxide layer.
摘要翻译：一种制造用于半导体器件的金属间介电层的方法。该方法包括形成间隔开的导线。接下来，在隔开的导线上形成第一共形氧化硅膜（阻挡层）。间隙或谷在被阻挡层覆盖的金属线之间。在第一氧化硅层上形成新的第一“间隙填充”旋涂玻璃层。在关键步骤中，第一SOG层被加热以回流，从而使所有第一旋涂玻璃层从金属线上方流出并将所有第一SOG层留在间隙中。随后，第二氧化硅层仅在间隙中沉积在第一氧化硅层上并且在第一旋涂玻璃层上方。然后在第二氧化硅层上形成第二自旋玻璃层。通过蚀刻回去并去除玻璃层上的整个第二自旋并且将第二氧化硅层部分来进行回蚀。最后，在第二氧化硅层上形成氧化硅或氮化硅的绝缘盖层。

148. 发明授权

US06180489B2 Formation of finely controlled shallow trench isolation for ULSI process 有权
标题翻译：形成用于ULSI工艺的精细控制的浅沟槽隔离
公开(公告)号：US06180489B2
公开(公告)日：2001-01-30
申请号：US09290922
申请日：1999-04-12
申请人： Fu-Liang Yang , Bih-Tiao Lin , Wei-Ray Lin , Erik S. Jeng
发明人： Fu-Liang Yang , Bih-Tiao Lin , Wei-Ray Lin , Erik S. Jeng
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A method for forming planarized shallow trench isolation is described. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide trench and at least one narrow trench. A first oxide layer is deposited over the first nitride layer and within the isolation trenches wherein the first oxide layer fills the isolation trenches. A capping nitride layer is deposited overlying the first oxide layer. A second oxide layer is deposited overlying the capping nitride layer. The second oxide layer is polished away wherein the second oxide layer and the capping nitride layer are left only within the wide trench. The first and second oxide layers are dry etched away with an etch stop on the capping nitride layer within the wide trench and the first nitride layer wherein the second oxide layer is completely removed. Thereafter, the first oxide layer is overetched to leave the top surface of the first oxide layer just above the bottom surface of the first nitride layer and the capping nitride layer within the wide trench. The capping nitride layer and the first nitride layer are removed completing the formation of shallow trench isolation regions in the fabrication of an integrated circuit device.
摘要翻译：描述了形成平坦化浅沟槽隔离的方法。在半导体衬底的表面上沉积氮化物层。通过氮化物层将多个隔离沟槽蚀刻到半导体衬底中，其中存在至少一个宽沟槽和至少一个窄沟槽。第一氧化物层沉积在第一氮化物层之上并且在隔离沟槽内，其中第一氧化物层填充隔离沟槽。覆盖第一氧化物层的覆盖氮化物层被沉积。覆盖覆盖氮化物层的第二氧化物层被沉积。抛光第二氧化物层，其中第二氧化物层和覆盖氮化物层仅留在宽沟槽内。第一氧化物层和第二氧化物层在宽沟槽内的覆盖氮化物层上的蚀刻停止层和第二氧化物层被完全去除的第一氮化物层被干蚀刻掉。此后，将第一氧化物层过蚀刻，以将第一氧化物层的顶表面刚好在第一氮化物层的底表面和宽沟槽内的覆盖氮化物层的上方。在制造集成电路器件时，去除覆盖氮化物层和第一氮化物层，从而形成浅沟槽隔离区。

149. 发明授权

US6159821A Methods for shallow trench isolation 有权
标题翻译：浅沟槽隔离方法
公开(公告)号：US6159821A
公开(公告)日：2000-12-12
申请号：US249255
申请日：1999-02-12
申请人： Hsu-Li Cheng , Wei-Ray Lin , Fu-Liang Yang
发明人： Hsu-Li Cheng , Wei-Ray Lin , Fu-Liang Yang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76264 , H01L21/76283
摘要： A method for forming self-rounded shallow trench isolation is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is then deposited overlying the pad oxide layer. Isolation trenches are then etched through the nitride and pad oxide layers into the semiconductor substrate. A layer of oxide is then deposited over the said nitride layer and within the isolation trenches. The oxide layer is then polished away through chemical and mechanical polishing wherein the substrate is planarized. The nitride layer is then etched away using a special dry-etch recipe that has a higher etching rate for silicon nitride than oxide. The dry-etch recipe also has a very low etching rate for the silicon substrate. This results in the removal of the nitride layer, rounding the shoulders of the trench and leaving the substrate unaffected. The fabrication of the integrated circuit device is completed.
摘要翻译：描述了形成自圆浅浅沟槽隔离的方法。衬垫氧化物层设置在半导体衬底的表面上。然后将氮化物层沉积在衬垫氧化物层上。然后将隔离沟槽通过氮化物和衬垫氧化物层蚀刻到半导体衬底中。然后将一层氧化物沉积在所述氮化物层上并在隔离沟槽内。然后通过化学和机械抛光将氧化物层抛光，其中基底被平坦化。然后使用特别的干蚀刻配方蚀刻氮化物层，其具有比氧化物更高的氮化硅蚀刻速率。干蚀刻配方对于硅衬底也具有非常低的蚀刻速率。这导致氮化物层的去除，使沟槽的肩部四舍五入并且使衬底不受影响。完成集成电路器件的制造。

150. 发明授权

US6140240A Method for eliminating CMP induced microscratches 有权
标题翻译：消除CMP诱导显微镜的方法
公开(公告)号：US6140240A
公开(公告)日：2000-10-31
申请号：US226275
申请日：1999-01-07
申请人： Fu-Liang Yang , Bih-Tiao Lin , Tzu-Shih Yen , Bi-Ling Chen , Erik S. Jeng
发明人： Fu-Liang Yang , Bih-Tiao Lin , Tzu-Shih Yen , Bi-Ling Chen , Erik S. Jeng
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/302
CPC分类号： H01L21/31053 , H01L21/31138
摘要： A method of removing microscratches in planarized dielectric surfaces covering conductor layers in submicron integrated circuit structures includes a semiconductor substrate having at least one dielectric layer formed thereon followed by a chemical mechanical polishing process for planarization. The removal of microscratches includes depositing a PE-CVD polymer layer to fill the microscratches, caused by CMP planarization, and to cover the planarized dielectric surface with a thin layer of the polymer. Deposition is followed by introducing an etching gas into the CVD chamber for an etch back of the just deposited polymer to well below the depth of the microscratches wherein the deposited polymer has the same etch rate as the dielectric layer formed thereunder.
摘要翻译：在亚微米集成电路结构中的覆盖导体层的平坦化电介质表面中去除微结构的方法包括具有形成在其上的至少一个介电层，然后进行平面化的化学机械抛光工艺的半导体衬底。去除微观尺度包括沉积PE-CVD聚合物层以填充由CMP平坦化引起的微观尺度，并用聚合物薄层覆盖平坦化的电介质表面。沉积之后，将CVD蚀刻气体引入CVD室，以便正好沉积的聚合物的蚀刻深度远低于微细凹槽的深度，其中沉积的聚合物具有与其下形成的介电层相同的蚀刻速率。

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