会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 142. 发明授权
    • Graded collector for inductive loads
    • 用于感性负载的分级收集器
    • US5311054A
    • 1994-05-10
    • US674147
    • 1991-03-25
    • Glenn A. DeJongGregory J. ScottAkira Ito
    • Glenn A. DeJongGregory J. ScottAkira Ito
    • H01L21/331H01L21/74H01L29/08H01L29/36H01L29/72
    • H01L29/66272H01L21/74H01L29/0821H01L29/36
    • A bipolar transistor having an improved collector structure includes a buried region of the same conductivity type as the collector region spaced from the base region and having a laterally graded impurity concentration with the lowest below the center of the emitter region. An integrated circuit may include transistors having the buried collector region of the diminishing lateral impurity concentration below the center of its emitter as well as having transistors with a uniform lateral impurity concentration below the total lateral extent of the emitter. A method of achieving the unique collector region includes forming at least a first collector region of a first conductivity type as two lateral portions of substantially uniform lateral impurity concentration with a space therebetween in a substrate of a second conductivity type and heating to form the buried collector struture of diminishing lateral impurity concentration. This is followed by forming a collector layer on the substrate, forming a base region in the collector region and an emitter region in the base region over the space in the buried collector region. If the integrated circuit includes transistors which do not have the unique graded collector, the buried collector region for these transistors is formed by introducing impurities having substantially uniform lateral impurity concentration in the substrate.
    • 具有改进的集电极结构的双极晶体管包括与基极区域间隔开的集电极区域具有相同导电类型的掩埋区域,并且具有最低于发射极区域中心的最低的杂质浓度。 集成电路可以包括晶体管,其晶体管具有越来越小的横向杂质浓度低于其发射极中心的掩埋集电极区域,并且具有低于发射极的总横向范围的均匀横向杂质浓度的晶体管。 实现唯一的集电极区域的方法包括:在第二导电类型的衬底中形成至少第一导电类型的第一集电极区域作为具有基本上均匀的横向杂质浓度的两个横向部分,并且在第二导电类型的衬底中形成空间,并加热以形成埋设的集电器 横向杂质浓度越来越小。 接着在衬底上形成集电极层,在集电极区域中形成基极区域,在掩埋集电极区域的空间上形成基极区域中的发射极区域。 如果集成电路包括不具有唯一的梯度集电极的晶体管,则通过在衬底中引入具有基本均匀的横向杂质浓度的杂质来形成用于这些晶体管的掩埋集电极区域。
    • 143. 发明授权
    • Rear projection screen
    • 背投屏幕
    • US4921329A
    • 1990-05-01
    • US221531
    • 1988-07-19
    • Akira ItoMizuo Okada
    • Akira ItoMizuo Okada
    • G03B21/62G03B21/625
    • G03B21/625
    • Provided is a rear projection screen of a certain configuration having an entrance surface receiving red, blue and green rays from projectors on a projecting side and formed therein entrance lenses and an exit surface allowing images synthesized or merged with the red, blue and green light rays to be observed on a viewing side and formed therein exit lenses corresponding respectively to the incident lenses, each of the entrance lenses are each of the exit lenses having optical axes and lens surfaces around the optical axes, respectively, with theoretical curvatures so that each entrance lens transmits red, blue and green light rays to the corresponding exit lens while the entrance lens converges the light rays into a certain converging area around the cross point between the lens surface of the corresponding exit lens and the optical axis if the configuration of the screen is theoretical, and each associated exit lens emits the converged light rays from the exit surface toward the viewing side over a predetermined viewing angle, wherein the curvature of each exit lens is made to be moderate more than the theoretical curvature of the exit lens, outside of the converging area around the cross point between the lens surface and the optical axis of the exit lens.
    • 本发明提供一种具有一定形状的背投屏幕,其入射面从突出侧的投影仪接收红色,蓝色和绿色光线,并形成入射透镜和允许与红色,蓝色和绿色光线合成或合并的图像的出射面 在观察侧观察并在其上形成分别对应入射透镜的出射透镜,每个入射透镜分别具有围绕光轴的光轴和透镜表面的理论曲率,使得每个入口 透镜将红色,蓝色和绿色光线透射到相应的出射透镜,而入射透镜会将光线会聚到相应出射透镜的透镜表面与光轴之间的交叉点周围的某个会聚区域,如果屏幕的配置 是理论上的,并且每个相关联的出射透镜从出射表面朝向视图发射会聚的光线 其中每个出口透镜的曲率被制成比出射透镜的理论曲率更适度,在透镜表面和出射光轴之间的交叉点周围的会聚区域外侧 镜片。
    • 147. 发明授权
    • Reduction of parasitic capacitance in a semiconductor device
    • 降低半导体器件中的寄生电容
    • US09123807B2
    • 2015-09-01
    • US13019695
    • 2011-02-02
    • Akira Ito
    • Akira Ito
    • H01L29/66H01L29/78H01L29/10H01L29/45H01L29/49
    • H01L29/4983H01L29/1045H01L29/456H01L29/4933H01L29/7835
    • An apparatus is disclosed to increase a reduced a parasitic capacitance of a semiconductor device. The semiconductor device includes a modified gate region to effectively reduce an overlap capacitance and modified well regions to effectively reduce a junction capacitance. The modified gate region includes a doped region and an undoped to decrease an effective area of the overlap capacitance. The modified well regions are separated by a substantially horizontal distance to increase an effective distance of the junction capacitance. This decrease in the effective area of the overlap capacitance and this increase in the effective distance of the junction capacitance reduces the parasitic capacitance of the semiconductor device.
    • 公开了一种增加半导体器件的寄生电容降低的装置。 半导体器件包括修改的栅极区域,以有效地减少重叠电容和修改的阱区域以有效地减少结电容。 修改的栅极区域包括掺杂区域和未掺杂的,以减小重叠电容的有效面积。 改进的阱区域被分开大致水平的距离以增加结电容的有效距离。 重叠电容的有效面积的减小和结电容的有效距离的增加减小了半导体器件的寄生电容。