专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

131. 发明授权

US06788569B2 Thin film magnetic memory device reducing a charging time of a data line in a data read operation 失效
标题翻译：薄膜磁存储器件在数据读取操作中减少数据线的充电时间
公开(公告)号：US06788569B2
公开(公告)日：2004-09-07
申请号：US10259471
申请日：2002-09-30
申请人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C1100
CPC分类号： G11C11/15 , G11C11/16
摘要： During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.
摘要翻译：在数据读取期间，根据行和列选择操作，激活感测使能信号以在形成包括数据线的当前路径和所选择的存储器单元之前开始数据线的充电。早期完成数据线的充电，从而可以将开始数据读取所需的时间减少到数据线之间的通过电流差达到对应于所选存储单元的存储数据的电平的状态，并且可以快速执行数据读取。

132. 发明授权

US06738285B2 Thin film magnetic memory device with high-accuracy data read structure having a reduced number of circuit elements 失效
标题翻译：具有数量少的电路元件的具有高精度数据读取结构的薄膜磁存储器件
公开(公告)号：US06738285B2
公开(公告)日：2004-05-18
申请号：US10190668
申请日：2002-07-09
申请人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C1100
CPC分类号： G11C11/16
摘要： In a data read operation, a selected memory cell and a reference memory cell are connected to complementary first and second data lines via complementary first and second bit lines, respectively. A differential amplifier supplies passing currents of the memory cell and the reference cell to complementary first and second data buses, and amplifies a passing current difference between the first and second data buses occurring corresponding to an electric resistance difference between the memory cell and reference cell to produce a voltage difference of a polarity corresponding to the level of the stored data of the selected memory cell between first and second nodes.
摘要翻译：在数据读取操作中，选择的存储单元和参考存储单元分别经由互补的第一和第二位线连接到互补的第一和第二数据线。差分放大器将存储单元和参考单元的通过电流提供给互补的第一和第二数据总线，并且将与存储单元和参考单元之间的电阻差对应的第一和第二数据总线之间的通过电流差放大到产生与第一和第二节点之间的所选存储单元的存储数据的电平相对应的极性的电压差。

133. 发明授权

US06628554B2 MIS semiconductor device having improved gate insulating film reliability 失效
公开(公告)号：US06628554B2
公开(公告)日：2003-09-30
申请号：US09813796
申请日：2001-03-22
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C700
CPC分类号： G11C11/413 , G11C8/08
摘要： A reliability evaluation value of a gate insulating film of an insulated gate type (MIS) transistor in an unselected state is set to a value equal to or smaller than the reliability evaluation value of the gate insulating film of the MIS transistor in a selected state. An electric field applied to the gate insulating film is determined in accordance with the reliability evaluation value. Therefore, it is possible to the gate insulating film applied electric field of the MIS transistor in the unselected state lower than the electric field in the selected state to assure the reliability of the gate insulating film of the MIS transistor in the unselected state. Thus, the reliability of the gate insulating film of the MIS transistor in the unselected state is assured, and a semiconductor device with an improved gate dielectric characteristics.

134. 发明授权

US06603217B2 Semiconductor circuit device having hierarchical power supply structure 有权
公开(公告)号：US06603217B2
公开(公告)日：2003-08-05
申请号：US09967939
申请日：2001-10-02
申请人： Tsukasa Ooishi , Hideto Hidaka
发明人： Tsukasa Ooishi , Hideto Hidaka
IPC分类号： H02J100
CPC分类号： G11C5/063 , G11C5/14 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y10T307/391 , Y10T307/461 , Y10T307/696 , Y10T307/724 , Y10T307/747
摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

135. 发明授权

US06587371B1 Memory device having wide margin of data reading operation, for storing data by change in electric resistance value 有权
标题翻译：具有大量数据读取操作的存储器件，用于通过改变电阻值来存储数据
公开(公告)号：US06587371B1
公开(公告)日：2003-07-01
申请号：US09944346
申请日：2001-09-04
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C1114
CPC分类号： G11C11/15
摘要： Read word lines are disposed in correspondence with rows of memory cells arranged in a matrix, and bit lines and reference voltage lines are disposed in correspondence with the columns. A data read current is passed through a current path passing a selected memory cell, which is formed between a data read circuit and a read reference voltage via a data bus, a column selection gate, a bit line, and a reference voltage line. The data read circuit detects a voltage change occurring in the selected memory cell due to the data read current and outputs read data. A sum of an electric resistance value of the bit line and an electric resistance value of the reference voltage line in a portion included in the current path is set to be almost constant without depending on a row to which the selected memory cell belongs.
摘要翻译：读取字线与排列成矩阵的存储单元的行对应配置，位线和基准电压线与列对应配置。数据读取电流通过经由经由数据总线，列选择栅极，位线和参考电压线在数据读取电路和读取参考电压之间形成的选定存储单元的电流路径。数据读取电路检测由于数据读取电流而在所选存储单元中发生的电压变化，并输出读取数据。将包括在当前路径中的部分中的位线的电阻值和参考电压线的电阻值之和设置为几乎恒定，而不依赖于所选存储单元所属的行。

136. 发明授权

US06501679B2 Thin film magnetic device including memory cells having a magnetic tunnel junction 有权
标题翻译：薄膜磁存储器件包括具有磁性隧道结的存储单元
公开(公告)号：US06501679B2
公开(公告)日：2002-12-31
申请号：US10066558
申请日：2002-02-06
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C1115
CPC分类号： G11C7/12 , G11C7/14 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C2207/002
摘要： In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.
摘要翻译：在数据读取操作中，存储器单元和虚拟存储单元分别耦合到所选位线对的两个位线，并且向其提供数据读取电流。在选择的存储单元列中，根据位线上的相应电压，读取门驱动读取数据总线对上的相应电压。数据读取电路放大读取数据总线之间的电压差，以输出读取数据。读取门的使用使读取数据总线能够与数据读取当前路径断开连接。结果，快速地产生位线上的各个电压变化，从而可以提高数据读取速度。

137. 发明授权

US06445222B1 Data output circuit with reduced output noise 失效
标题翻译：数据输出电路具有降低的输出噪声
公开(公告)号：US06445222B1
公开(公告)日：2002-09-03
申请号：US09708509
申请日：2000-11-09
申请人： Hideto Hidaka , Masakazu Hirose
发明人： Hideto Hidaka , Masakazu Hirose
IPC分类号： H03K300
CPC分类号： H03K19/00361
摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.
摘要翻译：当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。当驱动晶体管导通时，输出节点以高速放电到地电位。当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。结果，输出节点的电位从高电平降低到中间电平，使得随后的输出信号的幅度减小。提供了可以有效地防止产生振铃而不增加访问时间的输出电路。提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。高速提供稳定的输出信号。

138. 发明授权

US06414894B2 Semiconductor device with reduced current consumption in standby state 失效
标题翻译：半导体器件在待机状态下具有降低的电流消耗
公开(公告)号：US06414894B2
公开(公告)日：2002-07-02
申请号：US09778062
申请日：2001-02-07
申请人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
发明人： Tsukasa Ooishi , Takaharu Tsuji , Masatoshi Ishikawa , Hideto Hidaka , Hiroshi Kato
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.
摘要翻译：逻辑部分向DRAM部分输出指示存储区域的起始地址和结束地址，其中存储的数据在转换到具有降低的电流消耗的掉电模式之前存在。在断电模式中，刷新控制单元保存起始地址和结束地址，并且仅在需要刷新的区域中控制要进行数据刷新。逻辑部分的电源在掉电模式下被设置为断开状态，因此半导体器件可以在保持数据的同时消耗电流。

139. 发明授权

US06404661B2 Semiconductor storage device having arrangement for controlling activation of sense amplifiers 有权
标题翻译：具有用于控制感测放大器的激活的装置的半导体存储装置
公开(公告)号：US06404661B2
公开(公告)日：2002-06-11
申请号：US09464793
申请日：1999-12-16
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C506
CPC分类号： G11C5/14
摘要： A memory cell array includes a plurality of memory cells that are arranged in the row and column directions. Power supply lines and grounding lines are arranged on the memory cell array so as to extend in the column direction. The grounding lines are so arrayed that a plurality of power supply lines are interposed therebetween or, conversely, the power supply lines are so arranged that a plurality of grounding lines are interposed therebetween. By connecting together adjacent power supply lines (or grounding lines) of the same potential on a column decoder to form a single power line, the number of power supply lines extending in the column direction on the column decoder can be reduced, whereby an effective element forming region of the column decoder can be expanded.
摘要翻译：存储单元阵列包括沿列和列方向布置的多个存储单元。电源线和接地线布置在存储单元阵列上，以便在列方向上延伸。接地线如此排列，使得多个电源线插入其间，或者相反地，电源线布置成使得多个接地线插入其间。通过将列解码器上相同电位的相邻电源线（或接地线）连接在一起形成单个电源线，可以减少在列解码器上沿列方向延伸的供电线的数量，从而有效元件可以扩展列解码器的形成区域。

140. 发明授权

US06313695B1 Semiconductor circuit device having hierarchical power supply structure 有权
标题翻译：具有分层电源结构的半导体电路装置
公开(公告)号：US06313695B1
公开(公告)日：2001-11-06
申请号：US09301359
申请日：1999-04-29
申请人： Tsukasa Ooishi , Hideto Hidaka
发明人： Tsukasa Ooishi , Hideto Hidaka
IPC分类号： G05F110
CPC分类号： G11C5/063 , G11C5/14 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y10T307/391 , Y10T307/461 , Y10T307/696 , Y10T307/724 , Y10T307/747
摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.
摘要翻译：电阻元件插入主电源线和主接地线，使得偏移差分放大器接收在其上产生的电压。差分放大器控制连接到副电源线和次接地线的晶体管。因此，从副电源线流向主接地线并从主电源线流向副接地线的漏电流规则地保持恒定。因此，可以在保持具有分层供电结构的半导体电路装置中降低亚阈值泄漏电流的效果的同时防止在待机状态的初始阶段的操作延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式