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    • 132. 发明授权
    • Low complexity multiple bits matched filter
    • 低复杂度多位匹配滤波器
    • US06426982B1
    • 2002-07-30
    • US09398939
    • 1999-09-17
    • Lin YangYan ZhongKevin Hwang
    • Lin YangYan ZhongKevin Hwang
    • H03D100
    • G06F17/15H04B1/707H04B7/195H04B2201/70707H04L27/2278H04L2027/0065
    • Method and system for efficiently and quickly forming a sequence of convolution values from an over-sampled digital signal sequence. Convolution value differences are computable from a set of digital signal values that is smaller than the original set of signal values by a factor of R, the over-sampling rate. The number of adders and the associated time delay for computation of the convolution differences are reduced by at least a factor R and by at least a factor approximately proportional to log2(R), respectively, as compared to conventional computation of a convolution value. This approach is used to estimate a time value for which the convolution attains a largest magnitude or value.
    • 用于从过采样数字信号序列有效且快速地形成卷积值序列的方法和系统。 卷积值差异可以从一组数字信号值计算,该组数字信号值小于原始信号值集合乘以R的倍数,即过采样率。 与卷积值的常规计算相比,用于计算卷积差的加法器的数量和相关联的时间延迟分别减少至少一个因子R和至少一个与log 2(R)成比例的因子。 该方法用于估计卷积达到最大幅度或值的时间值。
    • 134. 发明授权
    • Canonical signed two's complement constant multiplier compiler
    • 规范的二进制补码常数乘法器编译器
    • US5313414A
    • 1994-05-17
    • US976164
    • 1992-11-12
    • Lin YangChun-Ling Liu
    • Lin YangChun-Ling Liu
    • G06F7/00G06F17/50G06F7/52
    • G06F17/5045G06F7/00
    • A constant multiplier compiler model allows a modified canonical signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a modified canonical signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor signed two's complement constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. The number of zeros in the multi-bit constant is first maximized by converting the constant to modified canonical form. Then, for each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most significant bit of the multi-bit multiplicand and logic zero. The method produces a minimum layout, minimizing silicon cost, and produces a high performance design with critical paths optimized in terms of time delay.
    • 常数乘法器编译器模型允许从用户规定的期望常数生成经修改的规范有符号二进制补码常数乘法器电路设计。 用于计算多位被乘数和多位常数的乘积的经修改的规范有符号二进制补码常数乘法器电路的网表通过修改前导符号二进制补码常数乘法器电路的网表来自动生成,用于计算 多位被乘数和多位常数,全为1。 通过将常数转换为修改的规范形式,多位常数中的零数首先最大化。 然后,对于多比特常数中的每个零,删除相应的完整加法器的逻辑列,并且如此删除的每个加法器的每个输出信号在逻辑上连接到前面的加法器逻辑列中的相应输出信号。 发生上述规则的两个例外。 在没有加法器的先前逻辑列的加法器的第一逻辑列的情况下,删除的每个加法器的每个输出信号逻辑上连接到多位被乘数的位。 在接收到多位被乘数的最高有效位的逻辑加法器行的情况下,删除的每个加法器的每个输出信号逻辑地连接到多位被乘数和逻辑零的最高有效位之一。 该方法产生最小布局,最大限度地降低硅成本,并产生具有在时间延迟方面优化的关键路径的高性能设计。