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131. 发明授权

US09825005B2 Semiconductor package with Pillar-Top-Interconnection (PTI) configuration and its MIS fabricating method 有权
公开(公告)号：US09825005B2
公开(公告)日：2017-11-21
申请号：US14960962
申请日：2015-12-07
申请人： POWERTECH TECHNOLOGY INC.
发明人： Yun-Hsin Yeh , Hung-Hsin Hsu
IPC分类号： H01L25/04 , H01L23/31 , H01L23/48 , H01L25/065 , H01L23/00 , H01L23/498 , H01L21/683 , H01L25/00 , H01L21/48 , H01L21/56 , H01L25/10
CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/481 , H01L23/49838 , H01L24/17 , H01L24/81 , H01L25/105 , H01L25/50 , H01L2221/68345 , H01L2221/68359 , H01L2224/16145 , H01L2224/16227 , H01L2224/16245 , H01L2224/81005 , H01L2224/81191 , H01L2225/06524 , H01L2225/06548 , H01L2225/1023 , H01L2225/1029 , H01L2924/1511 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/1815
摘要： Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a plurality of metal pillars disposed on the RDL, a chip bonded onto the RDL, and a molding core. The molding core is formed on the carrier plane and has a bottom surface defined by the carrier plane so that the RDL is embedded inside the molding core. The package thickness of the molding core is greater than the chip-bonding height of the chip so that the chip is completely embedded inside the molding core. The metal pillars are encapsulated at the peripheries of the molding core with a plurality of pillar top portions exposed from the molding core. The exposed pillar top portions are reentrant from a top surface of the molding core and uneven. Accordingly, it realizes the effects of ultra-thin and smaller footprint POP stacked assembly with fine pitch vertically electrical connections in POP structure. Also, it is possible to achieve zero spacing between POP stacked assembly.

132. 发明申请

US20170309597A1 MANUFACTURING METHOD OF PACKAGE STRUCTURE 有权
公开(公告)号：US20170309597A1
公开(公告)日：2017-10-26
申请号：US15491982
申请日：2017-04-20
申请人： Powertech Technology Inc.
发明人： Yong-Cheng Chuang , Kuo-Ting Lin , Li-Chih Fang , Chia-Jen Chou
IPC分类号： H01L25/065 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3135 , H01L23/49816 , H01L23/5384 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/82 , H01L24/97 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/0237 , H01L2224/02373 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49109 , H01L2224/73265 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06548 , H01L2225/06558 , H01L2225/06562 , H01L2225/06572 , H01L2225/06586 , H01L2924/15311 , H01L2924/1815 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00012 , H01L2924/00014 , H01L2224/81 , H01L2224/83 , H01L2224/85 , H01L2924/00
摘要： A manufacturing method of a package structure includes at least the following steps. At least one first die is disposed over a carrier. The first die is encapsulated using a first encapsulant. The first encapsulant exposes part of the first die. A redistribution layer (RDL) is formed over the first encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first surface faces the first encapsulant. The first encapsulant and the first die are separated from the carrier. A plurality of second dies are disposed on the second surface of the RDL. The second dies are encapsulated using the second encapsulant. A plurality of conductive terminals are formed on the first surface of the RDL.

133. 发明授权

US09673178B2 Method of forming package structure with dummy pads for bonding 有权
公开(公告)号：US09673178B2
公开(公告)日：2017-06-06
申请号：US14970558
申请日：2015-12-16
申请人： Powertech Technology Inc.
发明人： Chia-Hsiang Yuan , Chia-Wei Chang , Kuo-Ting Lin , Yong-Cheng Chuang
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00
CPC分类号： H01L25/0657 , H01L24/03 , H01L24/06 , H01L24/20 , H01L24/45 , H01L24/85 , H01L25/50 , H01L2224/04042 , H01L2224/06505 , H01L2224/12105 , H01L2224/214 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/92224 , H01L2225/06506 , H01L2225/06562 , H01L2225/1035 , H01L2225/1058
摘要： Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

134. 发明申请

US20170084513A1 SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20170084513A1
公开(公告)日：2017-03-23
申请号：US15369802
申请日：2016-12-05
申请人： Powertech Technology Inc.
发明人： Shou-Chian Hsu , Hiroyuki Fujishima
IPC分类号： H01L23/367 , H01L23/00 , H01L23/31
CPC分类号： H01L23/3675 , H01L21/4846 , H01L21/486 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L23/3114 , H01L23/36 , H01L23/42 , H01L23/49816 , H01L24/02 , H01L24/12 , H01L24/19 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68345 , H01L2221/68372 , H01L2224/0233 , H01L2224/0236 , H01L2224/02381 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/3511
摘要： A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

135. 发明授权

US09412703B1 Chip package structure having a shielded molding compound 有权
标题翻译：具有屏蔽模塑料的芯片封装结构
公开(公告)号：US09412703B1
公开(公告)日：2016-08-09
申请号：US14623517
申请日：2015-02-17
申请人： Powertech Technology Inc.
发明人： Chien-Wen Huang , Ming-Hung Chang
IPC分类号： H01L23/00 , H01L23/552 , H01L23/31 , H01L23/498 , H01L23/29
CPC分类号： H01L23/552 , H01L23/3121 , H01L23/3128 , H01L23/488 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L24/16 , H01L24/32 , H01L24/48 , H01L2224/04042 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/1421 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2224/45099 , H01L2924/00
摘要： A chip package structure including a main substrate, a carrier substrate, at least a chip, a molding compound, a shielding layer and a plurality of connection structures between the main substrate and the carrier substrate. The shielding layer covers the top surface and the sidewalls of the molding compound and a portion of the carrier substrate. The shielding layer is electrically grounded through the connection structures.
摘要翻译：一种芯片封装结构，包括在主衬底和载体衬底之间的主衬底，载体衬底，至少芯片，模塑料，屏蔽层和多个连接结构。屏蔽层覆盖模制化合物的顶表面和侧壁以及载体基底的一部分。屏蔽层通过连接结构电接地。

136. 发明授权

US09379043B1 TSV structure having insulating layers with embedded voids 有权
标题翻译： TSV结构具有带嵌入空隙的绝缘层
公开(公告)号：US09379043B1
公开(公告)日：2016-06-28
申请号：US14618790
申请日：2015-02-10
申请人： POWERTECH TECHNOLOGY INC.
发明人： Ming-Yi Wang , Chao-Shun Chiu , Yen-Chu Chen
IPC分类号： H01L21/76 , H01L29/49 , H01L23/48 , H01L23/00 , H01L23/532 , H01L23/31 , H01L21/764 , H01L21/768
CPC分类号： H01L23/481 , H01L21/764 , H01L21/7682 , H01L21/76898 , H01L23/3171 , H01L24/11 , H01L24/13 , H01L29/4991 , H01L2221/1047 , H01L2224/11462 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2924/01082 , H01L2924/01047 , H01L2924/00014 , H01L2924/014
摘要： Disclosed is a TSV structure having insulating layers with embedded voids, including a chip layer, a dielectric liner and a conductive filler. There is at least a via reentrant from one surface of the semiconductor body of the chip layer. A plurality of air-gap cavities are formed on the sidewall of the via where the cavities have a depth-to-width ratio not less than one. The dielectric liner covers the sidewall of the via without filling into the air-gap cavities. The conductive filler is disposed in the via without filling into the air-gap cavities due to the isolation of the dielectric liner so as to form an air insulating layer with a plurality of enclosed voids embedded between the semiconductor body and the dielectric liner. Accordingly, RC Delay of the TSV structure can be improved.
摘要翻译：公开了具有包含芯片层，电介质衬垫和导电填料的具有嵌入空隙的绝缘层的TSV结构。从芯片层的半导体主体的一个表面至少存在通孔折返。在通孔的侧壁上形成有多个气隙腔，其中空腔具有不小于1的深度 - 宽度比。电介质衬垫覆盖通孔的侧壁而不填充到气隙腔中。导电填料由于绝缘衬垫的隔离而设置在通孔中，而不会填充到气隙腔中，从而形成具有嵌入在半导体本体和电介质衬垫之间的多个封闭空隙的空气绝缘层。因此，可以提高TSV结构的RC延迟。

137. 发明授权

US08980694B2 Fabricating method of MPS-C2 package utilized form a flip-chip carrier 有权
标题翻译：使用MPS-C2封装的制造方法形成倒装芯片载体
公开(公告)号：US08980694B2
公开(公告)日：2015-03-17
申请号：US13238828
申请日：2011-09-21
申请人： Shou-Chian Hsu
发明人： Shou-Chian Hsu
IPC分类号： H01L21/00 , H01L21/56 , H01L23/00 , H05K3/30
CPC分类号： H01L21/563 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/13082 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/27005 , H01L2224/27312 , H01L2224/29011 , H01L2224/29012 , H01L2224/2929 , H01L2224/29386 , H01L2224/32225 , H01L2224/73204 , H01L2224/8114 , H01L2224/81191 , H01L2224/81815 , H01L2224/83192 , H01L2224/83862 , H01L2224/92125 , H01L2924/15787 , H01L2924/3511 , H05K3/305 , H05K2201/10674 , H05K2201/10977 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/05442 , H01L2924/014
摘要： Disclosed are a flip-chip carrier having individual pad masks (IPMs) and a fabricating method of a MPS-C2 package utilized from the same. The flip-chip carrier primarily comprises a substrate and a plurality of the IPMs. The substrate has a top surface and a plurality of connecting pads on the top surface. The IPMs cover the corresponding connecting pads in one-on-one alignment where each IPM consists of a photo-sensitive adhesive layer on the corresponding connecting pad and a pick-and-place body pervious to light formed on the photo-sensitive adhesive layer. After the photo-sensitive adhesive layers are irradiated by light penetrating through the pick-and-place bodies, the pick-and-place bodies can be pulled out by a pick-and-place process to expose the connecting pads from an encapsulant. The issues of solder bridging and package warpage can easily be solved in conventional MPS-C2 packages.
摘要翻译：公开了一种具有独立焊盘掩模（IPM）的倒装芯片载体以及从其使用的MPS-C2封装的制造方法。倒装芯片载体主要包括基片和多个IPM。衬底具有顶表面和顶表面上的多个连接焊盘。 IPM以一对一对准方式覆盖对应的连接焊盘，其中每个IPM由相应的连接焊盘上的光敏粘合剂层和可透过光敏粘合剂层上形成的光的拾取和放置体组成。在通过穿透拾取物体的光照射光敏粘合剂层之后，可以通过拾取和放置工艺拉出拾取 - 放置物体，以将密封剂暴露于连接焊盘。焊接桥接和封装翘曲的问题可以在传统的MPS-C2封装中轻松解决。

138. 发明授权

US08546942B2 Flip-chip semiconductor device having anisotropic electrical interconnection and substrate utilized for the package 有权
标题翻译：具有用于封装的各向异性电互连和衬底的倒装芯片半导体器件
公开(公告)号：US08546942B2
公开(公告)日：2013-10-01
申请号：US13450188
申请日：2012-04-18
申请人： Hian-Hang Mah
发明人： Hian-Hang Mah
IPC分类号： H01L23/48
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/5382 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/13147 , H01L2224/16105 , H01L2224/16235 , H01L2224/16238 , H01L2224/17051 , H01L2224/17104 , H01L2224/8112 , H01L2224/81191 , H01L2224/81194 , H01L2224/81411 , H01L2224/81444 , H01L2224/81801 , H01L2224/81895 , H01L2224/81902 , H01L2924/01029 , H01L2924/15787 , H05K1/029 , H05K3/303 , H05K2201/10295 , H05K2201/10674 , H05K2203/173 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Disclosed is a flip-chip semiconductor device having isotropic electrical interconnection, primarily comprising a chip and a substrate. The chip has at least a first bump and a plurality of second bumps. The substrate has a plurality of bump pads disposed on the top surface and an isotropic connecting mechanism disposed inside the substrate consisting of a plurality of terminals electrically isolated from each other and a flexible vertical pad protruded from the top surface, wherein the disposition locations of the terminals circle around the flexible vertical pad as a disposition center. When the second bumps of the chip are bonded onto the corresponding bump pads, the first bump presses and bends the flexible vertical pad in a specific horizontal direction so that the flexible vertical pad selectively and electrically connect to a selected one of the terminals.
摘要翻译：公开了一种具有各向同性电互连的倒装芯片半导体器件，主要包括芯片和衬底。芯片具有至少第一凸块和多个第二凸块。衬底具有设置在顶表面上的多个凸块焊盘和设置在衬底内的各向同性连接机构，由多个彼此电隔离的端子和从顶表面突出的柔性垂直焊盘构成，其中，端子围绕柔性垂直焊盘围绕作为配置中心。当芯片的第二凸点接合到相应的凸块上时，第一凸块在特定的水平方向上按压并弯曲柔性垂直焊盘，使得柔性垂直焊盘选择性地和电连接到选定的端子之一。

139. 发明申请

US20120327729A1 MEMORY TESTING DEVICE HAVING CROSS INTERCONNECTIONS OF MULTIPLE DRIVERS AND ITS IMPLEMENTING METHOD 有权
标题翻译：具有多个驱动器的交叉连接的存储器测试装置及其实现方法
公开(公告)号：US20120327729A1
公开(公告)日：2012-12-27
申请号：US13421100
申请日：2012-03-15
申请人： Chih-Hui YEH
发明人： Chih-Hui YEH
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C2029/5602
摘要： Disclosed is a memory testing device having cross interconnections of multiple drivers, comprising a first wiring bus and a second wiring bus connected to a first device area and a third wiring bus and a fourth wiring bus connected to a second device area. A first I/O driver module bus is connected to the first wiring bus through a first driving bus. A second I/O driver module bus is connected to the third wiring bus through the second driving bus. The fourth wiring bus is Y-shaped connected to the node between the first wiring bus and first driving bus. And, the second wiring bus is Y-shaped connected to the node between the third wiring bus and the second driving bus.
摘要翻译：公开了具有多个驱动器的交叉互连的存储器测试装置，包括连接到第一装置区域的第一布线总线和连接到第二装置区域的第三布线总线和第四布线总线的第二布线总线。第一个I / O驱动器模块总线通过第一个驱动总线连接到第一个接线总线。第二个I / O驱动器模块总线通过第二个驱动总线连接到第三个接线总线。第四布线总线是Y形连接到第一布线总线和第一驱动总线之间的节点。而且，第二布线总线是Y形连接到第三布线总线和第二驱动总线之间的节点。

140. 发明授权

US08299587B2 Lead frame package structure for side-by-side disposed chips 有权
标题翻译：引线框架封装结构，并排布置芯片
公开(公告)号：US08299587B2
公开(公告)日：2012-10-30
申请号：US12764596
申请日：2010-04-21
申请人： Wen-Jeng Fan
发明人： Wen-Jeng Fan
IPC分类号： H01L23/495
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/49513 , H01L23/49551 , H01L24/48 , H01L24/49 , H01L2224/32245 , H01L2224/48247 , H01L2224/49109 , H01L2224/73265 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A lead frame package structure for side-by-side disposed chips including a lead frame, at least two chips, and a package material. The lead frame includes a plurality of inner leads; a plurality of outer leads; and at least two chip carrying areas having different horizontal levels. The chips are of different sizes and are respectively disposed on the chip carrying areas. The package material encapsulate the inner leads, the chip carrying areas and the chips, wherein the outer leads exposed out of the package material extend from the inner leads and have different horizontal levels.
摘要翻译：一种用于并排设置的芯片的引线框架封装结构，包括引线框架，至少两个芯片和封装材料。引线框架包括多个内引线; 多个外引线; 以及具有不同水平高度的至少两个芯片承载区域。芯片尺寸不同，分别设置在芯片承载区域上。封装材料封装内部引线，芯片承载区域和芯片，其中从封装材料暴露的外部引线从内部引线延伸并且具有不同的水平水平。

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