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121. 发明授权

US08976605B2 High voltage generation circuit and semiconductor device including the same 有权
标题翻译：高电压发生电路和包括其的半导体器件
公开(公告)号：US08976605B2
公开(公告)日：2015-03-10
申请号：US13549892
申请日：2012-07-16
申请人： Je Il Ryu
发明人： Je Il Ryu
IPC分类号： G11C7/00 , G05F3/02 , G11C5/14 , G11C8/08
CPC分类号： G11C5/145 , G11C7/00 , G11C8/08
摘要： A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a divided voltage, a section signal generation circuit configured to generate a plurality of section signals by comparing the divided voltage with each of different reference voltages, and a section signal combination circuit configured to generate enable signals for controlling the switches by combining the section signals.
摘要翻译：高电压发生电路包括被配置为产生最终泵电压的多个泵，被配置为将泵耦合到各个节点的多个开关;分压电路，被配置为将最终的泵电压与由开关互连的泵分开，并输出分压，分配信号生成电路，被配置为通过将分压电压与不同参考电压中的每一个进行比较来产生多个部分信号;以及部分信号组合电路，被配置为产生用于控制开关的使能信号，信号。

122. 发明申请

US20150054809A1 CIRCUIT FOR COMPENSATING A RIPPLE, METHOD OF DRIVING DISPLAY PANEL USING THE CIRCUIT AND DISPLAY APPARATUS HAVING THE CIRCUIT 有权
标题翻译：用于补偿纹理的电路，使用电路驱动显示面板的方法和具有电路的显示装置
公开(公告)号：US20150054809A1
公开(公告)日：2015-02-26
申请号：US14165942
申请日：2014-01-28
申请人： Samsung Display Co., LTD.
发明人： Woon-Yong LIM , Tong-Ill KWAK , Min-Ho PARK , Yong-Jin SHIN , Tae-Gwang JUNG , Bong-Kyun JO , Ki-Hyun PYUN
IPC分类号： G09G3/36 , G05F3/02
CPC分类号： G09G3/3696 , G09G3/3648 , G09G3/3655
摘要： A circuit includes a reference signal generating part configured to generate a plurality of reference signals having levels different from each other, a comparing part configured to compare a ripple signal with the reference signals to determine a level of the ripple signal, a compensating signal generating part configured to generate a compensation ripple signal corresponding to the level of the ripple signal, where the compensation ripple signal has a phase opposite to the ripple signal, and a push-pull circuit configured to stabilize the compensation ripple signal.
摘要翻译：电路包括：参考信号生成部，被配置为生成具有彼此不同的电平的多个参考信号;比较部，被配置为将纹波信号与参考信号进行比较，以确定纹波信号的电平;补偿信号生成部被配置为产生与纹波信号的电平相对应的补偿纹波信号，其中补偿纹波信号具有与纹波信号相反的相位，以及被配置为稳定补偿纹波信号的推挽电路。

123. 发明授权

US08963625B2 Semiconductor device driven by a main power supply voltage and an auxiliary power supply voltage 有权
标题翻译：半导体器件由主电源电压和辅助电源电压驱动
公开(公告)号：US08963625B2
公开(公告)日：2015-02-24
申请号：US14152406
申请日：2014-01-10
申请人： Renesas Electronics Corporation
发明人： Yuichiro Miwa , Masahiro Kitamura
IPC分类号： G05F3/02 , G06F1/26
CPC分类号： G05F3/02 , G06F1/263 , Y10T307/305 , Y10T307/391 , Y10T307/615 , Y10T307/724
摘要： A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V1
摘要翻译：微型计算机包括耦合在主电源端子和电源节点之间的第一开关以及耦合在辅助电源端子和电源节点之间的第二开关。微型计算机将主电源端子的电压V1与参考电压VR1进行比较。当V1> VR1时，微型电脑打开第一个开关并关闭第二个开关，当V1

124. 发明授权

US08941437B2 Bias circuit 有权
标题翻译：偏置电路
公开(公告)号：US08941437B2
公开(公告)日：2015-01-27
申请号：US14189780
申请日：2014-02-25
申请人： Fujitsu Limited
发明人： Hiroyuki Nakamoto
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/10 , G05F3/205
摘要： A bias circuit includes: a reference current generation circuit that has a first reference-current element disposed in a first current path and has a second reference-current element disposed in a second current path; a first current mirror circuit that has a first transistor connected in series with the first reference-current element and has a second transistor connected in series with the second reference-current element; a third reference-current element disposed in a third current path disposed between the power supply terminal and the reference-current element; a third transistor connected in series with the third reference-current element; a bypass capacitor connected between the power supply terminal and a second node connected to a control terminal of the third transistor; an activation circuit connected to the first node; and a first switch connected between the first node and the second node.
摘要翻译：偏置电路包括：参考电流产生电路，其具有设置在第一电流路径中的第一参考电流元件，并且具有设置在第二电流路径中的第二参考电流元件; 第一电流镜电路，具有与第一参考电流元件串联连接的第一晶体管，并具有与第二参考电流元件串联连接的第二晶体管; 设置在设置在所述电源端子和所述基准电流元件之间的第三电流路径中的第三基准电流元件; 与第三参考电流元件串联连接的第三晶体管; 连接在电源端子和连接到第三晶体管的控制端子的第二节点之间的旁路电容器; 连接到第一节点的激活电路; 以及连接在第一节点和第二节点之间的第一开关。

125. 发明授权

US08933674B2 Switch controller, switch control method, and power supply device comprising the switch controller 有权
标题翻译：开关控制器，开关控制方式以及包括开关控制器的电源装置
公开(公告)号：US08933674B2
公开(公告)日：2015-01-13
申请号：US13677834
申请日：2012-11-15
申请人： Fairchild Korea Semiconductor Ltd.
发明人： Young-Je Lee , Gye-Hyun Cho , Jae-Yong Lee , Ji-Hoon Jang
IPC分类号： H02M3/156 , H02M7/12 , G05F3/02 , H02M7/217
CPC分类号： H02M7/12 , G05F3/02 , H02M7/217
摘要： The present invention relates to a switch controller, a switch control method, and a power supply including the switch controller. An exemplary embodiment of the present invention detects an on-time of a power switch of the power supply and decreases a frequency of a clock signal according to a period during which the detected on-time is shorter than or equal to the minimum on-time. According to the exemplary embodiment, switching of the power switch is controlled according to a clock signal, and the minimum on-time is an on period of the power switch that cannot be shortened.
摘要翻译：本发明涉及开关控制器，开关控制方法以及包括开关控制器的电源。本发明的一个示例性实施例检测电源的电源开关的接通时间，并且根据检测到的接通时间小于或等于最小接通时间的周期来降低时钟信号的频率。根据示例性实施例，根据时钟信号来控制电源开关的切换，并且最小接通时间是不能缩短的电源开关的接通周期。

126. 发明授权

US08928382B1 Multiple gate semiconductor devices and their applications 有权
公开(公告)号：US08928382B1
公开(公告)日：2015-01-06
申请号：US13832619
申请日：2013-03-15
申请人： Altera Corporation
发明人： Chun Lee Ler , Shuxian Chen , Jeffrey T. Watt
IPC分类号： H03H11/16 , H01L29/78 , G05F3/02 , H03H11/20
CPC分类号： H01L29/7855 , H01L27/0629 , H01L29/93 , H03H7/185 , H03H7/20
摘要： A multiple gate semiconductor structure is disclosed having a thin segment of semiconductor with first and second major surfaces that are opposite one another, a first gate on the first major surface of the segment, a second gate on the second major surface of the segment opposite the first gate, a first differential input coupled to the first gate, and a second differential input coupled to the second gate. Preferably the semiconductor structure is symmetrical about a plane that extends through the thin segment between the first and second major surfaces. When a first voltage of a first polarity is applied to the first input and a second voltage of the same magnitude as that of the first voltage but of opposite polarity is applied to the second input, a virtual ground is established in the structure near its center of the segment.

127. 发明授权

US08884602B2 Reference voltage circuit 有权
标题翻译：参考电压电路
公开(公告)号：US08884602B2
公开(公告)日：2014-11-11
申请号：US13780745
申请日：2013-02-28
申请人： Seiko Instruments Inc.
发明人： Fumiyasu Utsunomiya
IPC分类号： G05F3/16 , G05F3/20 , G05F1/10 , G05F3/02
CPC分类号： G05F3/02 , G05F3/242
摘要： A constant current flowing through a first depletion transistor whose gate and source are connected to each other is caused to flow through a second depletion transistor having the same threshold as the first depletion transistor, to thereby generate a first voltage between a gate and a source of the second depletion transistor. The constant current of the first depletion transistor and a constant current flowing through a third depletion transistor whose gate and source are connected to each other are caused to flow through a fourth depletion transistor. A threshold of the fourth depletion transistor is the same as that of the third depletion transistor but different from that of the first depletion transistor, and hence a second voltage is generated between a gate and a source of the fourth depletion transistor. A reference voltage is generated based on a voltage difference between the first and second voltages.
摘要翻译：流过其栅极和源极彼此连接的第一耗尽晶体管的恒定电流流过具有与第一耗尽晶体管相同的阈值的第二耗尽晶体管，从而在栅极和源极之间产生第一电压第二耗尽晶体管。使第一耗尽晶体管的恒定电流和流过栅极和源极彼此连接的第三耗尽晶体管的恒定电流流过第四耗尽晶体管。第四耗尽晶体管的阈值与第三耗尽晶体管的阈值相同，但不同于第一耗尽晶体管的阈值，因此在第四耗尽晶体管的栅极和源极之间产生第二电压。基于第一和第二电压之间的电压差产生参考电压。

128. 发明授权

US08878600B1 Internal voltage generation circuits 有权
标题翻译：内部电压发生电路
公开(公告)号：US08878600B1
公开(公告)日：2014-11-04
申请号：US14134271
申请日：2013-12-19
申请人： SK Hynix Inc.
发明人： Min Seok Choi
IPC分类号： G05F1/10 , G05F3/02 , H03K17/22
CPC分类号： G06F1/24 , G06F1/26 , G11C5/145 , H03K2217/0081
摘要： An internal voltage generation circuit includes a flag signal generator suitable for generating a first flag signal which is enabled after a first predetermined time from a moment that a deep power-down mode terminates and suitable for generating a second flag signal which is enabled after a second predetermined time from a moment that the first flag signal is enabled, a drive signal generator suitable for receiving the first and second flag signals to generate a first drive signal and a second drive signal and suitable for receiving a pre-oscillation signal in response to the first and second flag signals to generate a third drive signal and a fourth drive signal, and an internal voltage generator suitable for driving a first internal voltage signal in response to the first and second drive signals and suitable for pumping a second internal voltage signal in response to the third and fourth drive signals.
摘要翻译：内部电压产生电路包括一个标志信号发生器，适用于产生第一标志信号，该第一标志信号在从深度掉电模式终止之后的第一预定时间起使能，并且适于产生在第二标志信号之后使能的第二标志信号从第一标志信号被使能的时刻开始的预定时间，适于接收第一和第二标志信号的驱动信号发生器，以产生第一驱动信号和第二驱动信号，并且适于响应于第一标志信号接收预振荡信号第一和第二标志信号以产生第三驱动信号和第四驱动信号，以及内部电压发生器，其适于响应于第一和第二驱动信号驱动第一内部电压信号并且适于响应于泵浦第二内部电压信号到第三和第四驱动信号。

129. 发明授权

US08847674B1 Systems and methods for power limiting for a programmable I/O device 有权
标题翻译：用于可编程I / O设备的功率限制的系统和方法
公开(公告)号：US08847674B1
公开(公告)日：2014-09-30
申请号：US13801214
申请日：2013-03-13
申请人： General Electric Company
发明人： Daniel Milton Alley
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/16 , G05F3/04
摘要： A device includes a digital to analog converter (DAC) configured to generate a voltage output or a current output. The device also includes an integrated circuit configured to receive at least one of the voltage output or the current output and transmit the at least one of the voltage output or the current output to a load, wherein the integrated circuit is configured to measure a voltage level or a current level related to the transmission of the at least one of the voltage output or the current output. In one embodiment, a current limiter is included for voltage outputs as a form of power limiting and circuit protection. Additionally, the device includes a controller configured to receive an indication of the measurement from the integrated circuit and determine if the indication of the measurement exceeds a predetermined threshold.
摘要翻译：一种设备包括被配置为产生电压输出或电流输出的数模转换器（DAC）。该装置还包括集成电路，其被配置为接收电压输出或电流输出中的至少一个，并将电压输出或电流输出中的至少一个传送到负载，其中集成电路被配置为测量电压电平或与电压输出或电流输出中的至少一个的传输相关的电流电平。在一个实施例中，电流限制器被包括用于电压输出作为功率限制和电路保护的形式。此外，该设备包括控制器，其被配置为从集成电路接收测量的指示并且确定测量的指示是否超过预定阈值。

130. 发明申请

US20140247034A1 LOW SUPPLY VOLTAGE BANDGAP REFERENCE CIRCUIT AND METHOD 有权
标题翻译：低电压带对准电路和方法
公开(公告)号：US20140247034A1
公开(公告)日：2014-09-04
申请号：US13783423
申请日：2013-03-04
申请人： Hong Kong Applied Science and Technology Research Institute Company Limited
发明人： Chi Fung Lok , Le Feng Shen
IPC分类号： G05F3/02
CPC分类号： G05F3/02 , G05F3/30
摘要： A circuit and method for a bandgap voltage reference operating at 1 volt or below is disclosed, wherein the operational amplifier (A1) drives resistors (R2, R3) only so that both the flicker noise contribution and the process sensitivity due to the conventional metal oxide semiconductor (MOS) devices used as a current mirror within the proportional-to-absolute-temperature (PTAT) loop are eliminated. Two symmetric resistive divider pairs formed by (R1A/R1B, R2A/R2B) are inserted to scale down both the base-emitter voltages (VEB1, VEB2) of bipolar transistors (Q1, Q2) and the PTAT current (IPTAT) so that an output reference voltage (VREF) becomes scalable. Proper bias currents through transistors (M3, M4), which are used to bias (Q1, Q2) and (R1A/R1B, R2A/R2B) respectively, are produced by an additional V-I converter (319) using VREF itself, resulting in a final process, voltage and temperature (PVT) insensitive output reference voltage.
摘要翻译：公开了一种用于1伏特或更低电压工作的带隙电压基准的电路和方法，其中运算放大器（A1）仅驱动电阻器（R2，R3），使得由于常规金属氧化物而引起的闪烁噪声贡献和处理灵敏度消除了在比例绝对温度（PTAT）环路中用作电流镜的半导体（MOS）器件。插入由（R1A / R1B，R2A / R2B）形成的两个对称电阻分压器对，以缩小双极晶体管（Q1，Q2）和PTAT电流（IPTAT）的基极 - 发射极电压（VEB1，VEB2）输出参考电压（VREF）变得可扩展。分别用于偏置（Q1，Q2）和（R1A / R1B，R2A / R2B）的晶体管（M3，M4）的适当偏置电流由另外的VI转换器（319）使用VREF本身产生，导致最终过程，电压和温度（PVT）不敏感输出参考电压。

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