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121. 发明授权

US07532054B2 Semiconductor integrated circuit device having I/O circuitry for low voltage operation 有权
标题翻译：具有用于低压操作的I / O电路的半导体集成电路器件
公开(公告)号：US07532054B2
公开(公告)日：2009-05-12
申请号：US11405541
申请日：2006-04-18
申请人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
发明人： Yusuke Kanno , Kazuo Tanaka , Shunsuke Toyoshima , Takeo Toba
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H01L27/0928 , H01L27/105 , H03K3/356113
摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.
摘要翻译：提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元用于驱动主要大型缓冲区。鉴于此，高电压被施加到电平转换器和预缓冲器电路。通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

122. 发明申请

US20090050962A1 MOSFET WITH ISOLATION STRUCTURE FOR MONOLITHIC INTEGRATION AND FABRICATION METHOD THEREOF 有权
标题翻译：具有隔离结构的MOSFET用于单片集成及其制造方法
公开(公告)号：US20090050962A1
公开(公告)日：2009-02-26
申请号：US11913037
申请日：2005-10-14
申请人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu Lin , Ta-yung Yang
发明人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu Lin , Ta-yung Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/0928 , H01L21/823878 , H01L21/823892
摘要： A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors.
摘要翻译：提供了具有用于单片集成的隔离结构的MOSFET器件。 P型MOSFET包括设置在P型衬底中的第一N阱，设置在第一N阱中的第一P型区，设置在第一P型区中的P +漏极区，第一源电极形成有P +源极区域和N +接触区域。第一个N阱围绕着P +源极区域和N +接触区域。 N型MOSFET包括设置在P型衬底中的第二N阱，设置在第二N阱中的第二P型区，设置在第二N阱中的N +漏极区，第二源电极形成有N +源区和P +接触区。第二P型区围绕N +源极区域和P +接触区域。多个分离的P型区域设置在P型衬底中以提供晶体管的隔离。

123. 发明授权

US07449388B2 Method for forming multiple doping level bipolar junctions transistors 失效
标题翻译：用于形成多个掺杂级双极结晶体管的方法
公开(公告)号：US07449388B2
公开(公告)日：2008-11-11
申请号：US11458270
申请日：2006-07-18
申请人： Daniel Charles Kerr , Michael Scott Carroll , Amal Ma Hamad , Thiet The Lai , Roger W. Key
发明人： Daniel Charles Kerr , Michael Scott Carroll , Amal Ma Hamad , Thiet The Lai , Roger W. Key
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L27/0928 , H01L29/0821
摘要： A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.
摘要翻译：一种用于形成在半导体衬底上具有多个不同集电极掺杂密度的双极结型晶体管的工艺，以及包括具有多个不同集电极掺杂密度的双极结型晶体管的集成电路。第一组晶体管在形成三阱期间形成，用于为也形成在半导体衬底上的互补金属氧化物半导体场效应晶体管提供三阱隔离。在形成用于场效应晶体管的栅叠层之后的第二掺杂步骤期间，形成具有不同集电极掺杂密度的附加双极结型晶体管。通过双极晶体管发射极窗口进行的种植体掺杂形成了与先前形成的双极晶体管不同的掺杂密度的双极晶体管。根据本发明的一个实施例，形成具有六种不同集电极掺杂剂密度（并因此具有六种不同击穿特性）的双极结型晶体管。

124. 发明授权

US07445979B2 Method of fabricating isolated semiconductor devices in epi-less substrate 有权
标题翻译：在无外壳衬底中制造隔离半导体器件的方法
公开(公告)号：US07445979B2
公开(公告)日：2008-11-04
申请号：US11278771
申请日：2006-04-05
申请人： Richard K. Williams , Michael E. Cornell , Wai Tien Chan
发明人： Richard K. Williams , Michael E. Cornell , Wai Tien Chan
IPC分类号： H01L21/8238
CPC分类号： H01L21/26513 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L29/0878 , H01L29/1083 , H01L29/42368 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall and which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.
摘要翻译：通过将掺杂剂注入到不包括外延层的半导体衬底中来形成用于电绝缘半导体器件的结构。在植入后，该结构暴露于非常有限的热预算，使得掺杂剂不显着扩散。结果，隔离结构的尺寸受限制和限定，从而允许比使用包括外延层生长和掺杂剂扩散的常规工艺可获得更高的堆积密度。在一组实施例中，隔离结构包括深层和侧壁，并且它们一起形成围绕可以形成隔离半导体器件的封闭区域的杯形结构。侧壁可以由不同能量的一系列脉冲植入物形成，由此产生一叠重叠的注入区域。

125. 发明申请

US20080173948A1 SEMICONDUCTOR DEVICE AND COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
标题翻译：半导体器件和补充金属氧化物半导体场效应晶体管
公开(公告)号：US20080173948A1
公开(公告)日：2008-07-24
申请号：US11624693
申请日：2007-01-19
申请人： Shih-Kuei Ma , Chung-Yeh Lee , Chun-Ying Yeh , Wei-Ting Kuo
发明人： Shih-Kuei Ma , Chung-Yeh Lee , Chun-Ying Yeh , Wei-Ting Kuo
IPC分类号： H01L27/092
CPC分类号： H01L27/0921 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L27/0928 , H01L29/1083 , H01L29/1087 , H01L29/7835
摘要： A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.
摘要翻译：半导体器件包括衬底，外延层，沉降片，有源器件，第一掩埋层和第二掩埋层。衬底具有第一类型的导电性。外延层具有第二类型的导电性，并且位于基板上。沉降片具有第二类型的导电性，并且位于外延层中。沉降片从衬底延伸到外延层的上表面，并且将区域从外延层分隔开。有源设备位于该区域内。第一掩埋层具有第一类型的导电性，并且位于区域和衬底之间。第二掩埋层具有第二类型的导电性，并且位于第一埋层和衬底之间。第二埋层与沉降片连接。由于上述结构，可以防止闩锁。

126. 发明申请

US20080128756A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件，半导体器件和半导体器件制造方法
公开(公告)号：US20080128756A1
公开(公告)日：2008-06-05
申请号：US11952373
申请日：2007-12-07
申请人： Shigeo SATOH
发明人： Shigeo SATOH
IPC分类号： H01L23/48 , H01L21/82
CPC分类号： H01L27/0928 , H01L21/823892
摘要： A semiconductor device is provided with a first conductivity type semiconductor substrate (10); a voltage supplying terminal (26) arranged on the semiconductors substrate (10); one or more elements (6) which include a second conductivity type well section (22) and are arranged on the semiconductor substrate (10); a second conductivity type first conductive layer (21), which is a lower layer of the one or more elements (6), is in contact with the second conductivity type well section (22), and connects the second conductivity type well section (22) of the one or more elements (6) with the voltage supplying terminal (26); and a first conductivity type second conductive layer (11) formed in contact with a lower side of the first conductive layer (21).
摘要翻译：半导体器件设置有第一导电型半导体衬底（10）; 设置在所述半导体基板（10）上的电压供给端子（26）。一个或多个元件（6），其包括第二导电类型阱部分（22）并布置在半导体衬底（10）上; 作为所述一个以上元件（6）的下层的第二导电型第一导电层（21）与所述第二导电型阱部（22）接触，并且将所述第二导电型阱部（22））所述一个或多个元件（6）与所述电压供给端子（26）连接; 以及与第一导电层（21）的下侧接触形成的第一导电型第二导电层（11）。

127. 发明授权

US07365377B2 Semiconductor integrated circuit device using four-terminal transistors 失效
标题翻译：半导体集成电路器件采用四端子晶体管
公开(公告)号：US07365377B2
公开(公告)日：2008-04-29
申请号：US11166243
申请日：2005-06-27
申请人： Takeshi Sugahara , Yasuhito Itaka
发明人： Takeshi Sugahara , Yasuhito Itaka
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L21/823892 , H01L27/0203 , H01L27/0928
摘要： In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed in the semiconductor substrate excluding the region where the first well region has been formed. The third well region is formed under the first and second well regions in the semiconductor substrate in such a manner that a part of the third well region under the first well region is removed, thereby connecting the second well regions to one another electrically.
摘要翻译：在第一导电类型的半导体衬底中，形成第一导电类型的第一阱区，第二导电类型的第二阱区和第二导电类型的第三阱区。除了形成第一阱区的区域之外，在半导体衬底中形成第二阱区。第三阱区域形成在半导体衬底中的第一阱区和第二阱区之下，使得第一阱区下面的第三阱区的一部分被去除，从而将第二阱区彼此电连接。

128. 发明申请

US20080029824A1 ESD POWER CLAMP IN TRIPLE WELL 审中-公开
标题翻译：三相ESD ESD钳位
公开(公告)号：US20080029824A1
公开(公告)日：2008-02-07
申请号：US11461831
申请日：2006-08-02
申请人： Arnold E. Baizley , Philippe Hauviller , Steven H. Voldman
发明人： Arnold E. Baizley , Philippe Hauviller , Steven H. Voldman
IPC分类号： H01L29/76
CPC分类号： H01L27/0928 , H01L27/0266 , H01L27/0629 , H01L27/0808 , H01L29/78
摘要： A power clamp in a triple well is disclosed. A metal oxide semiconductor (MOS) varactor is used in a triggering circuit and is positioned in a first N type well. An N-channel field effect transistor is positioned in a P-type well. A P-channel field effect transistor is positioned in a second N-type well. The first N-type well is electrically isolated from the second N-type well, and electrically contacts the substrate of the power clamp.
摘要翻译：公开了三阱中的功率钳。金属氧化物半导体（MOS）变容二极管用于触发电路，并位于第一N型阱中。 N沟道场效应晶体管位于P型阱中。 P沟道场效应晶体管位于第二N型阱中。第一N型阱与第二N型阱电隔离，并与电源夹的基板电接触。

129. 发明申请

US20070252731A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20070252731A1
公开(公告)日：2007-11-01
申请号：US11785673
申请日：2007-04-19
申请人： Yi-Sun Chung
发明人： Yi-Sun Chung
IPC分类号： H03M7/00
CPC分类号： H01L27/0722 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0928
摘要： A semiconductor integrated circuit including digital circuits and analog circuits integrated over a single substrate includes the substrate including portions where the digital circuits and the analog circuits are to be formed, and a plurality of deep-wells formed to a certain thickness inside the substrate to surround portions where devices of the digital circuits and devices of the analog circuits are to be formed to reduce interference between the devices of the analog circuits and the digital circuits.
摘要翻译：包括集成在单个基板上的数字电路和模拟电路的半导体集成电路包括：基板，包括要形成数字电路和模拟电路的部分;以及在基板内形成一定厚度的多个深阱，要形成数字电路的设备和模拟电路的设备的部分，以减少模拟电路的设备与数字电路之间的干扰。

130. 发明授权

US07285453B2 Triple well structure and method for manufacturing the same 有权
标题翻译：三重井结构及其制造方法
公开(公告)号：US07285453B2
公开(公告)日：2007-10-23
申请号：US11474022
申请日：2006-06-23
申请人： Jih-Wei Liou
发明人： Jih-Wei Liou
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8238
CPC分类号： H01L27/0928 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： The present invention discloses a triple well structure, which includes a substrate of a first conductive type, a deep buried well of a second conductive type, a well of a first conductive type, a well ring of a second conductive type, and a well ring of a first conductive type. The deep buried well of the second conductive type is in the substrate. The well of the first conductive type is disposed over the deep buried well of the second conductive type in the substrate. The well ring of the second conductive type surrounds the well of the first conductive type. The well ring of the first conductive type is between the well of the first conductive type and the well ring of the second conductive type.
摘要翻译：本发明公开了一种三重阱结构，其包括第一导电类型的衬底，第二导电类型的深埋阱，第一导电类型的阱，第二导电类型的阱环和阱环的第一导电类型。第二导电类型的深埋井位于基板中。第一导电类型的阱设置在衬底中的第二导电类型的深埋阱上。第二导电类型的阱环围绕第一导电类型的阱。第一导电类型的阱环在第一导电类型的阱和第二导电类型的阱环之间。

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