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121. 发明申请

US20110242921A1 Systems And Methods Of Non-Volatile Memory Sensing Including Selective/Differential Threshold Voltage Features 有权
标题翻译：包括选择性/差分阈值电压特性的非易失性存储器感测的系统和方法
公开(公告)号：US20110242921A1
公开(公告)日：2011-10-06
申请号：US12750628
申请日：2010-03-30
申请人： Hieu Van Tran , Samar Saha
发明人： Hieu Van Tran , Samar Saha
IPC分类号： G11C7/06 , H01L29/792
CPC分类号： G11C7/065 , G11C7/06 , G11C7/062 , G11C16/28 , H01L21/28282 , H01L21/823412 , H01L21/823807 , H01L29/1083 , H01L29/42368 , H01L29/4238 , H01L29/66833 , H01L29/7835 , H01L29/792
摘要： Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.
摘要翻译：公开了用于通过使用具有差分阈值电压的MOS晶体管提供选择性阈值电压特性的系统和方法。在一个示例性实施例中，提供了一种金属氧化物半导体器件，其包括半导体材料的衬底，其具有源极区，漏极区和它们之间的沟道区，沟道区上方的绝缘层和绝缘层的栅极部。此外，关于器件，绝缘层的形状和/或接合区域的形状或注入在栅极 - 漏极和栅极 - 源极结之间具有不同的尺寸，以提供不同的阈值电压他们。

122. 发明申请

US20110169558A1 CHARGE PUMP SYSTEMS AND METHODS 有权
标题翻译：充电泵系统和方法
公开(公告)号：US20110169558A1
公开(公告)日：2011-07-14
申请号：US13070405
申请日：2011-03-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： G05F1/10
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.
摘要翻译：数字多电平存储器系统和方法包括用于为各种存储器操作产生调节的高电压的电荷泵。电荷泵可以包括多个泵级。示例性系统的方面可以包括在低电压操作条件下执行有序充电和放电的电荷泵。其他方面可以包括使状态状态泵送的特征，例如避免泵级之间的级联短路的电路。每个泵级还可以包括排放其节点的电路，例如通过相关联的泵互连通过自放电。另外的方面还可以包括以下功能：辅助各个泵级的上电，双电压，高电平移位，提供反并联电路配置和/或实现缓冲或预充电特征，例如自缓冲和自缓冲，预充电电路。

123. 发明申请

US20110121863A1 SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US20110121863A1
公开(公告)日：2011-05-26
申请号：US12972974
申请日：2010-12-20
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G11C7/08 , H03F3/45 , G11C7/06
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

124. 发明授权

US07848159B2 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US07848159B2
公开(公告)日：2010-12-07
申请号：US12275191
申请日：2008-11-20
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

125. 发明申请

US20100142272A1 METHOD AND APPARATUS FOR TESTING THE CONNECTIVITY OF A FLASH MEMORY CHIP 有权
标题翻译：用于测试闪存芯片连接性的方法和装置
公开(公告)号：US20100142272A1
公开(公告)日：2010-06-10
申请号：US12629302
申请日：2009-12-02
申请人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
发明人： Sang Thanh Nguyen , Hieu Van Tran , Hung O. Nguyen , Phil Klotzkin
IPC分类号： G11C16/04 , G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.
摘要翻译：在本发明的一个实施例中，用于连接测试的电路和硬件被制造在IC上，特别是包含闪存阵列的IC。该测试电路电连接到IC的接合焊盘。在一些实施例中，测试电路包括连接到每个接合焊盘的边界扫描单元，允许根据诸如JTAG标准的测试标准对闪存芯片进行快速连接测试。本发明还包括其中闪存芯片的引脚和/或存储单元被顺序发送一系列数据以测试IC的部分连通性的方法。然后检索顺序发送的数据并将其与原始数据进行比较。因此，这些数据集之间的差异突出了IC中的连接问题。

126. 发明申请

US20080224774A1 Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation 有权
标题翻译：用于多级闪存操作的系统和随机变化和不匹配补偿的方法和装置
公开(公告)号：US20080224774A1
公开(公告)日：2008-09-18
申请号：US12131008
申请日：2008-05-30
申请人： Hieu Van Tran , Hung Quoc Nguyen
发明人： Hieu Van Tran , Hung Quoc Nguyen
IPC分类号： H03F3/45
CPC分类号： G11C16/28 , G11C7/02 , G11C7/062 , G11C7/08 , G11C11/5642 , G11C16/30
摘要： Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
摘要翻译：公开了用于存储器感测系统的随机或系统失配补偿的方法和装置。感测放大器包括用于将感测晶体管的体积设置为不同于驱动感测晶体管的电压的电压的体电压源。对于NMOS感测晶体管，使用三重阱作为可变体电压。包括各种偏移补偿的差分放大器。有意义的意图偏移创建也包括在内。

127. 发明授权

US07403418B2 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US07403418B2
公开(公告)日：2008-07-22
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Van Tran , Jack Edward Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

128. 发明授权

US07342840B2 Single transistor sensing and double transistor sensing for flash memory 有权
标题翻译：用于闪存的单晶体管感测和双晶体管感测
公开(公告)号：US07342840B2
公开(公告)日：2008-03-11
申请号：US11602873
申请日：2006-11-20
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/06 , G11C7/062 , G11C7/12 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connection of the sensing transistor. Other sensing systems may use two transistors and may stores leakage current. A sensing system with capacitance auto-zeroing is included. The sensing system may include a dynamic differential current differential amplifier.
摘要翻译：单个感测晶体管被选择性地二极管连接到感测线，该感测线耦合到参考单元和数据单元，以通过打开开关来断开感测晶体管的二极管连接来在感测晶体管的栅极上存储参考电流或漏电流。其他感测系统可以使用两个晶体管并且可以存储泄漏电流。包含电容自动归零的感应系统。感测系统可以包括动态差分电流差分放大器。

129. 发明授权

US07139196B2 Sub-volt sensing for digital multilevel flash memory 有权
公开(公告)号：US07139196B2
公开(公告)日：2006-11-21
申请号：US10317433
申请日：2002-12-11
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (

130. 发明授权

US07035151B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US07035151B2
公开(公告)日：2006-04-25
申请号：US10868614
申请日：2004-06-14
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C8/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

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