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121. 发明授权

US08669608B2 Method for manufacturing nonvolatile semiconductor storage device and nonvolatile semiconductor storage device 有权
标题翻译：用于制造非易失性半导体存储装置和非易失性半导体存储装置的方法
公开(公告)号：US08669608B2
公开(公告)日：2014-03-11
申请号：US13419984
申请日：2012-03-14
申请人： Mitsuru Sato , Megumi Ishiduki , Masaru Kidoh , Atsushi Konno , Yoshihiro Akutsu , Masaru Kito , Yoshiaki Fukuzumi , Ryota Katsumata
发明人： Mitsuru Sato , Megumi Ishiduki , Masaru Kidoh , Atsushi Konno , Yoshihiro Akutsu , Masaru Kito , Yoshiaki Fukuzumi , Ryota Katsumata
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L21/265 , H01L27/11582 , H01L29/0676 , H01L29/66833
摘要： According to one embodiment, a method for manufacturing a nonvolatile semiconductor storage device includes; forming a first and a second stacked bodies; forming a through hole penetrating through the first stacked body, a second portion communicating with the first portion and penetrating through a select gate, and a third portion communicating with the second portion and penetrating through a second insulating layer; forming a memory film, a gate insulating film, and a channel body; forming a third insulating layer inside the channel body; forming a first embedded portion above a boundary portion inside the third portion; exposing the channel body by removing part of the first embedded portion and part of the third insulating layer in the third portion; and embedding a second embedded portion including silicon having higher impurity concentration than the first embedded portion above the first embedded portion inside the third portion.
摘要翻译：根据一个实施例，一种用于制造非易失性半导体存储装置的方法包括：形成第一和第二堆叠体; 形成穿过所述第一层叠体的通孔，与所述第一部分连通并穿过选择栅极的第二部分，以及与所述第二部分连通并穿透第二绝缘层的第三部分; 形成记忆膜，栅极绝缘膜和通道体; 在通道体内形成第三绝缘层; 在第三部分内部的边界部分上方形成第一嵌入部分; 通过去除第三部分中的第一嵌入部分和第三绝缘层的一部分的一部分来暴露通道体; 以及在所述第三部分内部嵌入包含比所述第一嵌入部分上方的所述第一嵌入部分杂质浓度高的硅的第二嵌入部分。

122. 发明授权

US09025377B2 Method of operating semiconductor memory device 有权
标题翻译：操作半导体存储器件的方法
公开(公告)号：US09025377B2
公开(公告)日：2015-05-05
申请号：US13052195
申请日：2011-03-21
申请人： Kunihiro Yamada , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Yoshiaki Fukuzumi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Kaori Kawasaki
发明人： Kunihiro Yamada , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Yoshiaki Fukuzumi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Kaori Kawasaki
IPC分类号： G11C16/22 , G11C16/04 , H01L27/115
CPC分类号： G11C16/0483 , G11C16/22 , H01L27/11578 , H01L27/11582
摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.
摘要翻译：根据一个实施例，公开了一种操作半导体存储器件的方法。该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

123. 发明授权

US08766351B2 Semiconductor storage device and manufacturing method of semiconductor storage device 有权
标题翻译：半导体存储装置及半导体存储装置的制造方法
公开(公告)号：US08766351B2
公开(公告)日：2014-07-01
申请号：US13112345
申请日：2011-05-20
申请人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
发明人： Takeshi Imamura , Yoshiaki Fukuzumi , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Kaori Kawasaki , Ryouhei Kirisawa
IPC分类号： H01L29/788
CPC分类号： H01L27/11556 , H01L29/42324 , H01L29/7889
摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.
摘要翻译：根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

124. 发明授权

US08598643B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08598643B2
公开(公告)日：2013-12-03
申请号：US13235425
申请日：2011-09-18
申请人： Kaori Kawasaki , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
发明人： Kaori Kawasaki , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层，绝缘构件和硅化物层。存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

125. 发明申请

US20120241846A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120241846A1
公开(公告)日：2012-09-27
申请号：US13235425
申请日：2011-09-18
申请人： Kaori KAWASAKI , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
发明人： Kaori KAWASAKI , Yoshiaki Fukuzumi , Masaru Kito , Tomoko Fujiwara , Takeshi Imamura , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层，绝缘构件和硅化物层。存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

126. 发明申请

US20120026775A1 METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：操作半导体存储器件的方法
公开(公告)号：US20120026775A1
公开(公告)日：2012-02-02
申请号：US13052195
申请日：2011-03-21
申请人： Kunihiro Yamada , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Yoshiaki Fukuzumi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Kaori Kawasaki
发明人： Kunihiro Yamada , Hideaki Aochi , Masaru Kito , Tomoko Fujiwara , Yoshiaki Fukuzumi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Kaori Kawasaki
IPC分类号： G11C17/12
CPC分类号： G11C16/0483 , G11C16/22 , H01L27/11578 , H01L27/11582
摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.
摘要翻译：根据一个实施例，公开了一种操作半导体存储器件的方法。该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

127. 发明申请

US20110147818A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110147818A1
公开(公告)日：2011-06-23
申请号：US12717499
申请日：2010-03-04
申请人： Ryota KATSUMATA , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
发明人： Ryota KATSUMATA , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
IPC分类号： H01L27/105
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction.
摘要翻译：非易失性半导体存储器件包括：衬底; 具有交替堆叠的多个绝缘膜和电极膜的存储器多层体，所述存储器多层体设置在所述衬底的存储器阵列区域上; 埋入存储器多层体中并在绝缘膜和电极膜的堆叠方向上延伸的半导体柱; 设置在所述电极膜和所述半导体柱之间的电荷存储膜; 具有多个绝缘膜和电极膜交替堆叠的虚设多层体和形成在其中的虚拟孔，所述虚设多层体设置在所述基板的外围电路区域上; 埋在虚拟孔中的绝缘构件; 以及埋入绝缘构件中并沿堆叠方向延伸的触点。

128. 发明授权

US08378406B2 Multilayer stacked type nonvolatile semiconductor memory device 有权
标题翻译：多层堆叠型非易失性半导体存储器件
公开(公告)号：US08378406B2
公开(公告)日：2013-02-19
申请号：US12717499
申请日：2010-03-04
申请人： Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
发明人： Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kidoh , Masaru Kito , Hideaki Aochi
IPC分类号： H01L29/76
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction.
摘要翻译：非易失性半导体存储器件包括：衬底; 具有交替堆叠的多个绝缘膜和电极膜的存储器多层体，所述存储器多层体设置在所述衬底的存储器阵列区域上; 埋入存储器多层体中并在绝缘膜和电极膜的堆叠方向上延伸的半导体柱; 设置在所述电极膜和所述半导体柱之间的电荷存储膜; 具有多个绝缘膜和电极膜交替堆叠的虚设多层体和形成在其中的虚拟孔，所述虚设多层体设置在所述基板的外围电路区域上; 埋在虚拟孔中的绝缘构件; 以及埋入绝缘构件中并沿堆叠方向延伸的触点。

129. 发明授权

US08338882B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08338882B2
公开(公告)日：2012-12-25
申请号：US12841662
申请日：2010-07-22
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.
摘要翻译：根据一个实施例，半导体存储器件包括基底，堆叠体，存储膜，通道体，互连和接触插塞。基底包括形成在基片的表面上的基片和外围电路。堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。记忆膜设置在通过层叠体冲压的存储孔的内壁上，以到达导电层的最下层。记忆膜包括电荷存储膜。互连设置在堆叠体的下方。互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。

130. 发明授权

US08253187B2 Non-volatile semiconductor storage device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储装置及其制造方法
公开(公告)号：US08253187B2
公开(公告)日：2012-08-28
申请号：US12142289
申请日：2008-06-19
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kido , Hideaki Aochi , Mitsuru Sato , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kido , Hideaki Aochi , Mitsuru Sato , Yasuyuki Matsuoka
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11556
摘要： A non-volatile semiconductor storage device 10 has a plurality of memory strings 100 with a plurality of electrically rewritable memory transistors MTr1-MTr4 connected in series. The memory string 100 includes a columnar semiconductor CLmn extending in a direction perpendicular to a substrate, a plurality of charge accumulation layers formed around the columnar semiconductor CLmn via insulating films, and selection gate lines on the drain side SGD contacting the columnar semiconductor to configure transistors. The selection gate lines on the drain side SGD have lower selection gate lines on the drain side SGDd, each of which is arranged with an interval with a certain pitch, and upper selection gate lines on the drain side SGDu located on a higher layer than the lower selection gate lines on the drain side SGDd, each of which is arranged on gaps between the lower selection gate lines on the drain side SGDd.
摘要翻译：非易失性半导体存储装置10具有多个串联连接的多个电可重写存储晶体管MTr1-MTr4的存储器串100。存储器串100包括沿垂直于衬底的方向延伸的柱状半导体CLmn，经由绝缘膜形成在柱状半导体CLmn周围的多个电荷累积层，以及与柱状半导体接触的漏极侧SGD上的选择栅极线，以配置晶体管。漏极侧SGD上的选择栅极线在漏极侧SGDd上具有较低的选择栅极线，每个栅极配置有一定间距的间隔，漏极侧SGDu上的选择栅极线位于高于漏极侧SGDd上的下部选择栅极线设置在漏极侧SGDd的下部选择栅极线之间的间隙。

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