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121. 发明申请

US20120187561A1 FORMING SEMICONDUCTOR CHIP CONNECTIONS 有权
标题翻译：形成半导体芯片连接
公开(公告)号：US20120187561A1
公开(公告)日：2012-07-26
申请号：US13432963
申请日：2012-03-28
申请人： Louis Lu-Chen Hsu , Kangguo Cheng , Timothy J. Dalton , Mukta G. Farooq , John A. Fitzsimmons
发明人： Louis Lu-Chen Hsu , Kangguo Cheng , Timothy J. Dalton , Mukta G. Farooq , John A. Fitzsimmons
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/14 , H01L21/6836 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L27/0207 , H01L29/0657 , H01L2224/0401 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/06183 , H01L2224/13009 , H01L2224/13099 , H01L2224/131 , H01L2224/14183 , H01L2224/16 , H01L2224/16105 , H01L2224/16137 , H01L2224/16147 , H01L2224/81205 , H01L2224/81801 , H01L2225/06513 , H01L2225/06524 , H01L2225/06551 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.
摘要翻译：公开了能够形成半导体芯片连接的系统和方法。在一个实施例中，半导体芯片包括具有一对相对侧面的多面体形状的主体; 以及沿着在多面体形状的一对相对侧之间延伸的一侧延伸的焊料构件。

122. 发明申请

US20120138571A1 PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL 有权
标题翻译：使用自组装材料的图案形成
公开(公告)号：US20120138571A1
公开(公告)日：2012-06-07
申请号：US12026123
申请日：2008-02-05
申请人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl Radens
发明人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl Radens
IPC分类号： B05D5/00 , B05D3/10 , B82Y40/00
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.
摘要翻译：在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的1/3。每个组中的六边形瓦片的开口形成在模板层中，并且在每个开口内施加并组合一组自组装嵌段共聚物。该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。在每组中以顺序的方式形成自组装的自对准线和空间结构，使得在超过有序范围的大面积上形成线和空间图案。

123. 发明授权

US08084825B2 Trilayer resist scheme for gate etching applications 有权
标题翻译：栅极蚀刻应用的三层抗蚀剂方案
公开(公告)号：US08084825B2
公开(公告)日：2011-12-27
申请号：US12245946
申请日：2008-10-06
申请人： Nicholas C. Fuller , Timothy J. Dalton , Ying Zhang
发明人： Nicholas C. Fuller , Timothy J. Dalton , Ying Zhang
IPC分类号： H01L29/78 , H01L27/088 , H01L20/10
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/28123
摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.
摘要翻译：提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

124. 发明授权

US08049335B2 System and method for plasma induced modification and improvement of critical dimension uniformity 有权
标题翻译：用于等离子体诱导修饰和改善临界尺寸均匀性的系统和方法
公开(公告)号：US08049335B2
公开(公告)日：2011-11-01
申请号：US11676674
申请日：2007-02-20
申请人： Timothy J. Dalton , Ronald A. Della Guardia , Nicholas C. Fuller
发明人： Timothy J. Dalton , Ronald A. Della Guardia , Nicholas C. Fuller
IPC分类号： H01L23/48
CPC分类号： H01L21/31138 , G03F7/40 , G03F7/405 , H01L21/0276 , H01L21/31144
摘要： Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved device performance, functionality and reliability.
摘要翻译：具有OSG或聚合物（90nm及以上的BEOL技术）的新型互连结构，其中采用先进的等离子体处理以减少半导体器件中的后平版印刷光盘不均匀性（“线边缘粗糙度”）。新颖的互连结构具有增强的衬垫和种子保形性，因此能够提供改进的设备性能，功能性和可靠性。

125. 发明授权

US08019970B2 Three-dimensional networking design structure 有权
标题翻译：三维网络设计结构
公开(公告)号：US08019970B2
公开(公告)日：2011-09-13
申请号：US11946422
申请日：2007-11-28
申请人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
发明人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
IPC分类号： G06F9/00
CPC分类号： H04L41/145
摘要： A design structure embodied in a machine readable medium used in a design process includes a multi-layer silicon stack architecture having one or more processing layers comprised of one or more computing elements; one or more networking layers disposed between the processing layers, the network layer comprised of one or more networking elements, wherein each computing element comprises a plurality of network connections to adjacently disposed networking elements and each networking element may provide network access to a plurality of other computing elements through a single hop of the network.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括具有由一个或多个计算元件组成的一个或多个处理层的多层硅堆叠架构; 布置在处理层之间的一个或多个网络层，网络层由一个或多个网络元件组成，其中每个计算元件包括多个网络连接到相邻布置的联网元件，并且每个网络元件可以提供对多个其他网络的网络访问通过网络的单跳计算元素。

126. 发明申请

US20100283121A1 ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS 有权
标题翻译：具有分层尺寸的电熔丝和电阻
公开(公告)号：US20100283121A1
公开(公告)日：2010-11-11
申请号：US12765275
申请日：2010-04-22
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

127. 发明申请

US20090138581A1 THREE-DIMENSIONAL NETWORKING DESIGN STRUCTURE 有权
标题翻译：三维网络设计结构
公开(公告)号：US20090138581A1
公开(公告)日：2009-05-28
申请号：US11946422
申请日：2007-11-28
申请人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
发明人： Kerry Bernstein , Timothy J. Dalton , Marc R. Faucher , Peter A. Sandon
IPC分类号： G06F15/173
CPC分类号： H04L41/145
摘要： A design structure embodied in a machine readable medium used in a design process includes a multi-layer silicon stack architecture having one or more processing layers comprised of one or more computing elements; one or more networking layers disposed between the processing layers, the network layer comprised of one or more networking elements, wherein each computing element comprises a plurality of network connections to adjacently disposed networking elements and each networking element may provide network access to a plurality of other computing elements through a single hop of the network.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括具有由一个或多个计算元件组成的一个或多个处理层的多层硅堆叠架构; 布置在处理层之间的一个或多个网络层，网络层由一个或多个网络元件组成，其中每个计算元件包括多个网络连接到相邻布置的联网元件，并且每个网络元件可以提供对多个其他网络的网络访问通过网络的单跳计算元素。

128. 发明申请

US20090014880A1 DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY 审中-公开
标题翻译：双重DAMASCENE工艺流程启用最小ULK膜修改和增强堆叠完整性
公开(公告)号：US20090014880A1
公开(公告)日：2009-01-15
申请号：US12236809
申请日：2008-09-24
申请人： Timothy J. Dalton , Nicholas C. Fuller , Satyanarayana V. Nitta
发明人： Timothy J. Dalton , Nicholas C. Fuller , Satyanarayana V. Nitta
IPC分类号： H01L23/532
CPC分类号： H01L21/76801 , H01L21/76808 , H01L21/76829
摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.
摘要翻译：本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂在灰化图案材料之前完成的阻挡层开口步骤。该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

129. 发明授权

US07427550B2 Methods of fabricating passive element without planarizing 有权
标题翻译：无平面化制造无源元件的方法
公开(公告)号：US07427550B2
公开(公告)日：2008-09-23
申请号：US11427457
申请日：2006-06-29
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

130. 发明申请

US20080175527A1 WAVEGUIDE POLARIZATION BEAM SPLITTERS AND METHOD OF FABRICATING A WAVEGUIDE WIRE-GRID POLARIZATION BEAM SPLITTER 有权
标题翻译：波导偏振光束分离器及波导波导极化分束器的制作方法
公开(公告)号：US20080175527A1
公开(公告)日：2008-07-24
申请号：US11870463
申请日：2007-10-11
申请人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstrom
发明人： Charles T. Black , Gian-Luca Bona , Timothy J. Dalton , Nicholas C. M. Fuller , Roland Germann , Maurice McGlashan-Powell , Chandrasekhar Narayan , Robert L. Sandstrom
IPC分类号： G02B6/00
CPC分类号： G02B6/126 , B29D11/00759 , G02B6/136 , G02B2006/1215
摘要： A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.
摘要翻译：实现在波导内传播的光的重定向并且消除波导的弯曲的必要性的方法或者涉及需要基本上小的半径的尖锐曲线的传播光的方向性变化中遇到的缺点，这将导致轻微的过度损失。在这方面，该方法涉及在光波导内制造和提供线栅偏振分束器，其利用二嵌段共聚物模板来配制线栅。

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