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111. 发明授权

US07038298B2 High fT and fmax bipolar transistor and method of making same 有权
标题翻译：高fT和fmax双极晶体管及其制造方法
公开(公告)号：US07038298B2
公开(公告)日：2006-05-02
申请号：US10604045
申请日：2003-06-24
申请人： Alvin Jose Joseph , Qizhi Liu
发明人： Alvin Jose Joseph , Qizhi Liu
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower portion. The base includes an intrinsic base (14) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高电平和高压双极晶体管（100）包括发射极（104），基极（120）和集电极（116）。发射器具有延伸超出下部的下部（108）和上部（112）。基部包括内在基极（14）和外部基极（144）。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体（148）。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括第二导体（152），其不延伸在发射极的上部下方，但是通过外部基极进一步减小电阻。

112. 发明授权

US07030462B2 Heterojunction bipolar transistor having specified lattice constants 失效
标题翻译：具有规定晶格常数的异质结双极晶体管
公开(公告)号：US07030462B2
公开(公告)日：2006-04-18
申请号：US10694889
申请日：2003-10-29
申请人： Motoji Yagura
发明人： Motoji Yagura
IPC分类号： H01L27/082
CPC分类号： H01L29/1004 , H01L29/0817 , H01L29/7371
摘要： A Heterojunction Bipolar Transistor, HBT, (100) containing a collector layer (104), a base layer (105) and an emitter layer (106) is constructed such that the collector layer (104), the base layer (105) and the emitter layer (106) have different lattice constants of ac, ab and ae respectively, and a value of ab between values of ac and ae (in other words, the values of ac, ab and ae satisfy a relationship of ac>ab>ae or ac
摘要翻译：包含集电极层（104），基极层（105）和发射极层（106）的异质结双极晶体管HBT（100）被构造为使得集电极层（104），基极层（105）和发射极层（106）分别具有不同的晶格常数，分别为a，b，a，b，的值之间（换句话说， / SUB>和一个＆lt;＆lt;＆lt;＆lt; /＆lt; /＆lt; /＆lt;＆lt; / SUB＆gt;满足＆lt; SUB＆gt; > c 根据本发明，可以实现具有高可靠性的HBT而不改变现有的用于生产HBT的设备和步骤。

113. 发明申请

US20060049485A1 High on-state breakdown heterojunction bipolar transistor 有权
标题翻译：高导通状态击穿异质结双极晶体管
公开(公告)号：US20060049485A1
公开(公告)日：2006-03-09
申请号：US11153078
申请日：2005-06-14
申请人： Noren Pan , Andree Wibowo
发明人： Noren Pan , Andree Wibowo
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/0817 , H01L29/0821 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) is provided with an improved on-state breakdown voltage VCE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.
摘要翻译：异质结双极晶体管（HBT）具有改进的导通状态击穿电压V CE。 HBT的导通状态击穿电压的改善提高了HBT的输出功率特性和HBT承受大阻抗失配（大VSWR）的能力。导通状态击穿电压的改善与抑制形成HBT的集电极区域的集电极层和副集电极层的接合附近的高电场有关。

114. 发明授权

US06989581B2 Wide band gap bipolar transistor with reduced thermal runaway 失效
标题翻译：宽带双极晶体管具有减少的热失控
公开(公告)号：US06989581B2
公开(公告)日：2006-01-24
申请号：US10497814
申请日：2002-12-23
申请人： Timothy Jonathan Phillips
发明人： Timothy Jonathan Phillips
IPC分类号： H01L27/082
CPC分类号： H01L29/66318 , H01L29/1004 , H01L29/7371
摘要： A bipolar transistor with vertical geometry comprises a base region (1) provided with a base contact (21), emitter and collector regions (2,3) arranged to extract minority carriers from the base region, and an excluding structure for counteracting entry of minority carriers into the base region via the base contact, wherein the base region has a bandgap of greater than 0.5 eV and a doping level greater than 1017 cm−3. As shown the base includes an excluding heterojunction (4) preventing entry of carriers from the base contact (21), but alternatively the base region could comprise a “high-low” doping homojunction. The construction shows improved resistance to thermal runaway even in multi-finger transistors. It is particularly useful for high power, high frequency transistors, e.g. base on gallium indium arsenide. The collector region preferably has a heterostructure.
摘要翻译：具有垂直几何形状的双极晶体管包括设置有基极触点（21）的基极区域（1），布置成从基极区域提取少数载流子的发射极和集电极区域（2,3），以及用于抵消少数进入的排除结构载体经由基极接触进入基极区域，其中基极区域具有大于0.5eV的带隙和大于10μS-3的掺杂水平。如图所示，底座包括防止载体从基极触点（21）进入的排除异质结（4），但是也可选择地，基极区域可以包括“高 - 低”掺杂均质结。该结构即使在多指状晶体管中也显示出改善的耐热失控性。它对于大功率高频晶体管是特别有用的。基于砷化铟镓。收集区优选具有异质结构。

115. 发明授权

US06979883B2 Integrated device in emitter-switching configuration and related manufacturing process 有权
标题翻译：集成器件在发射极开关配置和相关制造过程中
公开(公告)号：US06979883B2
公开(公告)日：2005-12-27
申请号：US10032289
申请日：2001-12-21
申请人： Sergio Tommaso Spampinato
发明人： Sergio Tommaso Spampinato
IPC分类号： H01L27/07 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L27/0761
摘要： An integrated device in emitter-switching configuration is described. The device is integrated in a chip of semiconductor material of a first conductivity type which has a first surface and a second surface opposite to each other. The device comprises a first transistor having a base region, an emitter region and a collector region, a second transistor having a not drivable terminal for collecting charges which is connected with the emitter terminal of the first transistor, a quenching element of the first transistor which discharges current therefrom when the second transistor is turned off. The quenching element comprises at least one Zener diode made in polysilicon which is coupled with the base terminal of the first transistor and with the other not drivable terminal of the second transistor. The at least one polysilicon Zener diode is formed on the second surface of said chip and it comprises a polysilicon layer having at least one zone of the first conductivity type and at least one zone of a second conductivity type in order to form at least one P-N junction.
摘要翻译：描述了发射器 - 开关配置中的集成器件。该器件集成在第一导电类型的半导体材料芯片中，该半导体材料具有彼此相对的第一表面和第二表面。该器件包括具有基极区域，发射极区域和集电极区域的第一晶体管，具有用于收集与第一晶体管的发射极端子连接的电荷的不可驱动端子的第二晶体管，第一晶体管的猝灭元件，当第二晶体管截止时，从其中释放电流。淬火元件包括至少一个由多晶硅制成的齐纳二极管，其与第一晶体管的基极端子和第二晶体管的另一个不可驱动的端子耦合。所述至少一个多晶硅齐纳二极管形成在所述芯片的第二表面上，并且其包括具有至少一个第一导电类型区域和至少一个第二导电类型区域的多晶硅层，以形成至少一个PN 交界处

116. 发明授权

US06977426B1 Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate 失效
标题翻译：半导体装置包括设置在单个基板上的高速晶体管和高压晶体管
公开(公告)号：US06977426B1
公开(公告)日：2005-12-20
申请号：US08965286
申请日：1997-11-06
申请人： Takayuki Gomi , Hiroaki Ammo
发明人： Takayuki Gomi , Hiroaki Ammo
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L27/06 , H01L29/732 , H01L29/00 , H01L27/082
CPC分类号： H01L21/8222
摘要： In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N+-type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
摘要翻译：在包括形成在通过在硅衬底上形成外延层而制成的半导体衬底上的不同电压的第一双极晶体管和第二双极晶体管的半导体器件中，在硅衬底的上部中，第一双极晶体管具有N < 具有比外延层高的杂质浓度的第一嵌入扩散层和第二双极晶体管具有N型第二嵌入扩散层，其具有较低的杂质浓度和较深的扩散层深度第一嵌入式扩散层，由此在相同的衬底上形成高速双极晶体管和高电压双极晶体管。

117. 发明申请

US20050265069A1 Merged mos-bipolar capacitor memory cell 有权
标题翻译：合并的MOS双极电容记忆体
公开(公告)号：US20050265069A1
公开(公告)日：2005-12-01
申请号：US11176992
申请日：2005-07-08
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： G11C7/00 , G11C11/24 , G11C11/34 , G11C11/405 , H01L21/336 , H01L27/082 , H01L27/102 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/109 , H01L31/113 , H01L31/119
CPC分类号： H01L27/108 , G11C11/405 , H01L27/0705 , H01L27/1023 , H01L27/10802 , H01L27/10823 , H01L29/7841
摘要： A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and a collector region. The base region for the vertical bi-polar transistor serves as the source region for the vertical MOS transistor. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical MOS transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor. The base region for the vertical bi-polar transistor is coupled to a write data word line.
摘要翻译：实现了用于DRAM操作的高密度垂直并联MOS双极电容器增益单元。增益单元包括其间具有源极区，漏极区和浮体区的垂直MOS晶体管。增益单元包括具有发射极区域，基极区域和集电极区域的垂直双极晶体管。垂直双极晶体管的基极区域用作垂直MOS晶体管的源极区域。栅极与浮体区域相对，并且由垂直MOS晶体管的第一侧上的栅极氧化物分离。浮体背栅对准垂直晶体管的第二侧上的浮体区域。用于垂直双极晶体管的基极区域耦合到写入数据字线。

118. 发明申请

US20050263851A1 Transistor assembly and method for manufacturing same 有权
标题翻译：晶体管组件及其制造方法
公开(公告)号：US20050263851A1
公开(公告)日：2005-12-01
申请号：US11127765
申请日：2005-05-11
申请人： Jakob Huber
发明人： Jakob Huber
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/082 , H01L29/00 , H01L29/06 , H01L29/732
CPC分类号： H01L29/7322 , H01L29/0692
摘要： A transistor assembly having a transistor includes a plurality of transistor regions, each of which has a vertical transistor structure having a collector semiconductor region, a base semiconductor region and an emitter semiconductor region, emitter contacting regions arranged above the transistor regions and base contacting regions connected to the base semiconductor regions via a polycrystalline semiconductor layer, wherein the polycrystalline semiconductor layer is structured such that the base contacting regions of transistor regions which are not part of the transistor are electrically isolated from base contacting regions of transistor regions which are part of the transistor.
摘要翻译：具有晶体管的晶体管组件包括多个晶体管区域，每个晶体管区域具有具有集电极半导体区域的垂直晶体管结构，基极半导体区域和发射极半导体区域，配置在晶体管区域上方的发射极接触区域和连接的基极接触区域通过多晶半导体层到基底半导体区域，其中多晶半导体层被构造成使得不是晶体管的一部分的晶体管区域的基极接触区域与作为晶体管的一部分的晶体管区域的基极接触区域电隔离。

119. 发明授权

US06967144B1 Low doped base spacer for reduction of emitter-base capacitance in bipolar transistors with selectively grown epitaxial base 有权
标题翻译：用于减少具有选择性生长的外延基极的双极晶体管中发射极 - 基极电容的低掺杂基极间隔物
公开(公告)号：US06967144B1
公开(公告)日：2005-11-22
申请号：US10669045
申请日：2003-09-23
申请人： Alexei Sadovnikov
发明人： Alexei Sadovnikov
IPC分类号： H01L21/331 , H01L27/082 , H01L27/102 , H01L29/10 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66242 , H01L29/1004
摘要： A bipolar transistor structure includes a collector region having a first conductivity type formed in a semiconductor substrate. A base region is formed over the collector region; the base region includes a highly doped lower layer having a second conductivity type opposite the first conductivity type formed on the collector region and a relatively low doped (or undoped) upper layer formed on the highly doped lower layer. An emitter region having the first conductivity type is formed on the upper layer of the base region.
摘要翻译：双极晶体管结构包括在半导体衬底中形成的具有第一导电类型的集电极区域。在集电极区域上形成基极区域; 基极区域包括具有与集电极区域上形成的第一导电类型相反的第二导电类型的高度掺杂的下层，以及形成在高掺杂的下层上的相对较低的掺杂（或未掺杂的）上层。具有第一导电类型的发射极区域形成在基极区域的上层。

120. 发明申请

US20050218399A1 Method of fabrication sige heterojunction bipolar transistor 有权
标题翻译：制造奇异异质结双极晶体管的方法
公开(公告)号：US20050218399A1
公开(公告)日：2005-10-06
申请号：US10515763
申请日：2003-05-27
申请人： Petrus Magnee , Johannes Josephus Donkers
发明人： Petrus Magnee , Johannes Josephus Donkers
IPC分类号： H01L21/331 , H01L29/732 , H01L29/737 , H01L29/06 , H01L21/8222 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L31/11 , H01L31/117
CPC分类号： H01L29/66242
摘要： The present invention provides for a method of fabricating a semiconductor device comprising a non-selectively grown SiGe(C) heterojunction bipolar transistor including the steps of forming an insulating layer (12, 40) on a substrate and providing a layer structure including a conductive layer (14, 42) on the insulating layer (12, 40), etching a transistor area opening (12, 44) through the conductive layer (14, 42), depositing a SiGe base layer (24, 46) on the inner wall of the transistor area opening (22, 44) and forming an insulator (32, 52) on an upper surface so as to fill the transistor area opening wherein prior to the filling step, a nitride layer (30, 50) is formed as an inner layer of the transistor area opening (22, 44).
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件包括非选择性生长的SiGe（C）异质结双极晶体管，包括以下步骤：在衬底上形成绝缘层（12,40），并提供包括导电层（14,42），通过所述导电层（14,42）蚀刻晶体管区域开口（12,44），在所述绝缘层（12,40）的内壁上沉积SiGe基底层（24,46）所述晶体管区域开口（22,44）并且在上表面上形成绝缘体（32,52）以便填充晶体管区域开口，其中在填充步骤之前，将氮化物层（30,50）形成为内部晶体管区域开口（22,44）的层。

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