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111. 发明授权

US06709962B2 Process for manufacturing printed circuit boards 失效
标题翻译：印刷电路板制造工艺
公开(公告)号：US06709962B2
公开(公告)日：2004-03-23
申请号：US10183574
申请日：2002-06-27
申请人： N. Edward Berg
发明人： N. Edward Berg
IPC分类号： H01L2144
CPC分类号： H05K3/061 , H05K1/0266 , H05K3/0079 , H05K3/108 , H05K3/1275 , H05K2203/0113 , H05K2203/013 , H05K2203/0517 , H05K2203/0534 , H05K2203/0783 , H05K2203/105 , H05K2203/1173 , H05K2203/1545 , H05K2203/1572 , H05K2203/163
摘要： A method for producing printed circuits utilizing direct printing methods to apply a pattern mask to a substrate. The direct printing methods include correcting positional errors in a printing apparatus by ascertaining the errors in the printer through comparison of a printed pattern and a known standard pattern. Printer inputs are manipulated to compensate for the ascertained errors of the printer. The pattern mask applied by the corrected printer may be an etch resist mask for forming conductive pathways by an etching process, or the pattern mask may be a plating mask with conductive pathways being formed by a plating operation. The process of the present invention is applicable to forming both single-sided and double-sided printed circuit boards.
摘要翻译：一种使用直接印刷方法制造印刷电路的方法，用于将图案掩模施加到基板上。直接打印方法包括通过比较打印图案和已知标准图案来确定打印机中的错误来校正打印装置中的位置错误。操作打印机输入以补偿确定的打印机错误。由校正的打印机施加的图案掩模可以是用于通过蚀刻工艺形成导电路径的抗蚀剂掩模，或者图案掩模可以是具有通过电镀操作形成的导电路径的电镀掩模。本发明的方法可用于形成单面和双面印刷电路板。

112. 发明授权

US06709894B2 Semiconductor package and method for fabricating the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US06709894B2
公开(公告)日：2004-03-23
申请号：US10170665
申请日：2002-06-12
申请人： Chung-Che Tsai , Wei-Heng Shan , Huan-Ping Su
发明人： Chung-Che Tsai , Wei-Heng Shan , Huan-Ping Su
IPC分类号： H01L2144
CPC分类号： H01L25/0652 , H01L24/45 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83194 , H01L2224/97 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.
摘要翻译：提供半导体封装及其制造方法。多个第一芯片安装在基板上并电连接到基板。包括屏蔽部分和支撑部分的屏蔽结构安装在基板上，其中支撑部分抵靠基板，并且屏蔽部分形成有与第一芯片相对应的多个开口。通过开口施加粘合剂以在第一芯片上分别形成粘合剂层。在从基板移除屏蔽结构之后，将多个第二芯片分别堆叠在粘合剂层上并电连接到基板。通过进行成形和分割工艺，将封装结构单个化以形成单独的半导体封装。以间歇形式形成粘合剂层的特征在于使制造成本和时间显着降低。

113. 发明授权

US06709889B2 Smart card module and method of assembling the same 失效
标题翻译：智能卡模块及其组装方法
公开(公告)号：US06709889B2
公开(公告)日：2004-03-23
申请号：US10270814
申请日：2002-10-15
申请人： Kiron P. Gore , Kevin Haas
发明人： Kiron P. Gore , Kevin Haas
IPC分类号： H01L2144
CPC分类号： G06K19/07747 , G06K19/07745 , H01L23/3121 , H01L23/49855 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/85399 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , Y10T29/49117 , Y10T29/4913 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A module (10) for use with a smart card (50) is disclosed. The module (10) includes a substrate (14) having a first side (16) and a second side (18). The first and second sides each have deposited thereon a metallic layer (19, 21), with the substrate (14) having a thickness of about 125 microns. A die (22) is mounted adjacent the substrate first side (16), with the die (22) being coupled to the substrate first side (16) by a plurality of wire leads (24). A protective coating (26) covers the die (22), with the module having a total thickness of about 525 microns.
摘要翻译：公开了一种与智能卡（50）一起使用的模块（10）。模块（10）包括具有第一侧（16）和第二侧（18）的衬底（14）。第一和第二面各自沉积有金属层（19,21），基底（14）具有约125微米的厚度。模具（22）安装在基板第一侧（16）附近，模具（22）通过多根引线（24）耦合到基板第一侧面（16）。保护涂层（26）覆盖模具（22），模块的总厚度约为525微米。

114. 发明授权

US06706630B1 Method for forming an alloyed metal conductive element of an integrated circuit 有权
标题翻译：用于形成集成电路的合金化金属导电元件的方法
公开(公告)号：US06706630B1
公开(公告)日：2004-03-16
申请号：US10376399
申请日：2003-02-28
申请人： Amit P. Marathe
发明人： Amit P. Marathe
IPC分类号： H01L2144
CPC分类号： H01L21/76886 , H01L21/02074 , H01L21/3212 , H01L21/76838
摘要： The introduction of alloying elements into a metal conductive element is achieved in situ in conjunction with a post-CMP reducing treatment. The source of the alloying elements may be a source gas introduced into the plasma chamber, or a source material incorporated into a post-CMP residue through presence in a CMP slurry or a post-CMP rinsing agent, or applied to the substrate prior to plasma treatment. The alloying element is introduced into the metal conductive element by diffusion during plasma treatment.
摘要翻译：将金属导电元件引入到原位与CMP后还原处理相结合。合金元素的来源可以是引入到等离子体室中的源气体，或通过存在于CMP浆料或后CMP漂洗剂中而掺入后CMP残留物的源材料，或者在等离子体之前施加到基板上治疗。在等离子体处理期间，通过扩散将合金元素引入金属导电元件。

115. 发明授权

US06706629B1 Barrier-free copper interconnect 有权
标题翻译：无障碍铜互连
公开(公告)号：US06706629B1
公开(公告)日：2004-03-16
申请号：US10338120
申请日：2003-01-07
申请人： Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
发明人： Jing-Cheng Lin , Cheng-Lin Huang , Winston Shue , Mong-Song Liang
IPC分类号： H01L2144
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76831 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76888 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.
摘要翻译：提供了一种新的方法来产生包括铜的金属互连。本发明的第一实施例提供了铜掺杂层的应用。本发明的第二个实施例提供了在介质层中形成的开口的表面上沉积作为隔离膜的氮化硅层，然后从开口的底部去除氮化硅层，随后沉积在该开口的表面上的铜掺杂合金种子层，然后在铜合金种子层上镀一层铜。

116. 发明授权

US06706627B2 Method of manufacturing capacitor with a diffusion barrier containing ruthenium, titanium and nitrogen 失效
标题翻译：制造具有含有钌，钛和氮的扩散阻挡层的电容器的方法
公开(公告)号：US06706627B2
公开(公告)日：2004-03-16
申请号：US10222684
申请日：2002-08-16
申请人： Dong-Soo Yoon
发明人： Dong-Soo Yoon
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , C23C16/34 , H01L21/28556 , H01L21/76855 , H01L21/76856 , H01L21/76862 , H01L21/7687 , H01L27/10855 , H01L28/55 , H01L28/65 , H01L28/75
摘要： A semiconductor device, including: a diffusion barrier layer composed of ternary compound elements formed on a substrate, wherein the diffusion barrier contains ruthenium, titanium and nitrogen; and a capacitor formed on the diffusion barrier layer, wherein the capacitor includes a bottom electrode formed on the diffusion barrier layer, a dielectric layer formed on the bottom electrode and a top electrode formed on the dielectric layer.
摘要翻译：一种半导体器件，包括：由形成在衬底上的三元化合物构成的扩散阻挡层，其中所述扩散阻挡层包含钌，钛和氮; 以及形成在所述扩散阻挡层上的电容器，其中所述电容器包括形成在所述扩散阻挡层上的底部电极，形成在所述底部电极上的电介质层和形成在所述电介质层上的顶部电极。

117. 发明授权

US06706622B1 Bonding pad interface 有权
标题翻译：键盘接口
公开(公告)号：US06706622B1
公开(公告)日：2004-03-16
申请号：US09949207
申请日：2001-09-07
申请人： John P. McCormick
发明人： John P. McCormick
IPC分类号： H01L2144
CPC分类号： H01L24/11 , H01L2224/05001 , H01L2224/05027 , H01L2224/0508 , H01L2224/05172 , H01L2224/05184 , H01L2224/05572 , H01L2224/13099 , H01L2924/01029 , H01L2924/01073 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2224/05644 , H01L2924/00014 , H01L2224/05147 , H01L2224/05155
摘要： A method for providing under bump metallization on a substrate. Trenches are formed in the substrate, and a layer of first electrically conductive material is formed over the substrate. The layer of the first electrically conductive material substantially fills the trenches and substantially covers the substrate between the trenches in a contiguous sheet. The layer of the first electrically conductive material is thinned to an end point where the layer of the first electrically conductive material is substantially reduced in thickness, but still forms the contiguous sheet between the trenches. A layer of photoresist is applied over the layer of the first electrically conductive material to define openings. A second electrically conductive material is deposited into the openings. The photoresist layer is removed, and the layer of the first electrically conductive material in the contiguous sheet between the trenches is removed to isolate the first electrically conductive material in the trenches. Because the layer of the first electrically conductive material is not completely removed in the areas between the trenches, the first electrically conductive material may be used as an electrode for the electroplate deposition of the second electrically conductive material. Thus, the under bump metallization can be produced in a more economical manner. If the layer of the first electrically conductive material were to be thinned to the point where the first electrically conductive material was only left in the trenches, then it would not be feasible to used the layer of the first electrically conductive material as an electrode, and thus it would further not be feasible to electroplate the second electrically conductive material.
摘要翻译：一种用于在衬底上提供凸块下金属化的方法。在衬底中形成沟槽，并且在衬底上形成第一导电材料层。第一导电材料的层基本上填充沟槽并基本上覆盖连续片材中沟槽之间的衬底。第一导电材料的层被薄化到第一导电材料层的厚度基本上减小的端点，但是仍然在沟槽之间形成连续的片材。在第一导电材料的层上施加一层光致抗蚀剂以限定开口。第二导电材料沉积到开口中。去除光致抗蚀剂层，并且移除在沟槽之间的邻接片材中的第一导电材料层，以隔离沟槽中的第一导电材料。因为第一导电材料的层在沟槽之间的区域中没有被完全去除，所以第一导电材料可以用作电极沉积第二导电材料的电极。因此，能够以更经济的方式制造凸块下金属化。如果将第一导电材料的层变薄到第一导电材料仅留在沟槽中的点，则将第一导电材料层用作电极是不可行的，以及因此电镀第二导电材料将不可行。

118. 发明授权

US06706621B2 Wafer integrated rigid support ring 有权
公开(公告)号：US06706621B2
公开(公告)日：2004-03-16
申请号：US10302412
申请日：2002-11-22
申请人： Harry D. Cox , David P. Daniel , Leonard J. Gardecki , Albert J. Gregoritsch, III , Ruth A. Machell Julianelle , Charles H. Keeler , Doris P. Pulaski , Mary A. Schaffer , David L. Smith , David J. Specht , Adolf E. Wirsing
发明人： Harry D. Cox , David P. Daniel , Leonard J. Gardecki , Albert J. Gregoritsch, III , Ruth A. Machell Julianelle , Charles H. Keeler , Doris P. Pulaski , Mary A. Schaffer , David L. Smith , David J. Specht , Adolf E. Wirsing
IPC分类号： H01L2144
CPC分类号： H01L23/528 , H01L23/544 , H01L24/10 , H01L24/11 , H01L24/13 , H01L2223/54406 , H01L2223/54493 , H01L2224/05001 , H01L2224/05022 , H01L2224/05111 , H01L2224/05124 , H01L2224/05147 , H01L2224/05171 , H01L2224/05568 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13611 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/0102 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/15787 , H01L2924/00014 , H01L2924/00
摘要： A shadow mask for depositing solder bumps includes additional dummy holes located adjacent holes corresponding to most of the perimeter chips of the wafer. The additional dummy provide more uniform plasma etching of contacts of the wafer, improve etching of contacts of perimeter chips, and lower contact resistance of contacts of perimeter chips. The extra holes also provide solder bumps outside the perimeter chips that can be used to support a second shadow mask for deposition of an additional material, such as tin, on the reflowed solder bumps for mounting the chips on a plastic substrate at low temperature. An improved mask to wafer alignment aid is formed from standard solder bumps. The improved alignment aid avoids damage to test probes and provides improved course alignment.

119. 发明授权

US06706560B2 Method of forming heat sink and semiconductor chip assemblies 有权
标题翻译：形成散热片和半导体芯片组件的方法
公开(公告)号：US06706560B2
公开(公告)日：2004-03-16
申请号：US10094300
申请日：2002-03-08
申请人： Joseph M. Brand
发明人： Joseph M. Brand
IPC分类号： H01L2144
CPC分类号： H01L23/4334 , H01L2924/0002 , H01L2924/00
摘要： Methods for applying a heat sink to a semiconductor chip. A heat sink frame is removably attached to one or more heat sinks and is used to align the heat sinks with corresponding semiconductor chips. The semiconductor chips are preferably positioned on a semiconductor chip frame. The heat sinks are aligned with the semiconductor chips either before or after the semiconductor chips are substantially encapsulated within a molding material. The heat sink frame is detached from the heat sinks at a selected time after the heat sinks and the semiconductor chips have been aligned, whereby the heat sinks remain combined with the semiconductor chips. Detachment of the heat sink frame may be conducted before or, alternatively, after the semiconductor chips have been encapsulated. The methods of the invention facilitates the efficient and reliable application of heat sinks to semiconductor chips.
摘要翻译：将散热器应用于半导体芯片的方法。散热器框架可移除地附接到一个或多个散热器，并且用于将散热器与对应的半导体芯片对准。半导体芯片优选地位于半导体芯片框架上。在半导体芯片基本上封装在模制材料中之前或之后，散热器与半导体芯片对齐。在散热器和半导体芯片已经对准之后的选定时间，散热器框架与散热器分离，由此散热器保持与半导体芯片的组合。散热器框架的分离可以在半导体芯片被封装之前或之后进行。本发明的方法有助于将散热器有效和可靠地应用于半导体芯片。

120. 发明授权

US06706557B2 Method of fabricating stacked die configurations utilizing redistribution bond pads 有权
标题翻译：使用再分布接合焊盘制造堆叠管芯配置的方法
公开(公告)号：US06706557B2
公开(公告)日：2004-03-16
申请号：US10422251
申请日：2003-04-24
申请人： Michel Koopmans
发明人： Michel Koopmans
IPC分类号： H01L2144
CPC分类号： H01L23/13 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/06135 , H01L2224/06136 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/48599 , H01L2224/731 , H01L2224/73215 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , Y10T29/49117 , Y10T29/49124 , Y10T29/49172 , Y10T29/49174 , Y10T29/49176 , Y10T29/49204 , Y10T29/49222 , Y10T83/0467 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/05599
摘要： A stacked semiconductor package including a plurality of stacked semiconductor devices on a substrate, and a method of forming the same. The semiconductor devices are stacked in an active surface-to-backside configuration. The top semiconductor die is flipped over to face the active surface of the semiconductor die directly below. An electrical connector can extend from a bond pad on the top semiconductor die to a redistribution circuit on the semiconductor die below. The redistribution circuit can be electrically connected to a substrate. Alternatively, an electrical connector extends from a bond pad on the top semiconductor die to a bond pad on a substrate.
摘要翻译：一种在衬底上包括多个层叠半导体器件的堆叠半导体封装及其形成方法。半导体器件以有源的表面到背面配置堆叠。顶部半导体管芯被翻转以直接在下方面对半导体管芯的有源表面。电连接器可以从顶部半导体管芯上的接合焊盘延伸到下面的半导体管芯上的再分配电路。再分布电路可以电连接到基板。或者，电连接器从顶部半导体管芯上的接合焊盘延伸到衬底上的接合焊盘。

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