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111. 发明授权

US07923787B2 MOSFET with isolation structure and fabrication method thereof 有权
标题翻译：具有隔离结构的MOSFET及其制造方法
公开(公告)号：US07923787B2
公开(公告)日：2011-04-12
申请号：US11913044
申请日：2005-10-14
申请人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu Lin , Ta-Yung Yang
发明人： Chih-Feng Huang , Tuo-Hsin Chien , Jenn-Yu Lin , Ta-Yung Yang
IPC分类号： H01L21/70
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928 , H01L29/1083 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.
摘要翻译：提供了具有隔离结构的MOSFET。 N型MOSFET包括设置在P型衬底中的第一N型掩埋层和P型外延层。 P型FET包括第二N型掩埋层和设置在P型衬底中的P型外延层。第一N型掩埋层和P型外延层提供FET之间的隔离。此外，设置在P型外延层中的多个分离的P型区域进一步提供隔离效果。在第一厚电场氧化物层和第一P型区域之间存在用于提高N型FET的击穿电压的第一间隙。在第二厚场氧化物层和第二N阱之间存在第二间隙，用于提高P型FET的击穿电压。

112. 发明授权

US07884440B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07884440B2
公开(公告)日：2011-02-08
申请号：US11785673
申请日：2007-04-19
申请人： Yi-Sun Chung
发明人： Yi-Sun Chung
IPC分类号： H01L21/70
CPC分类号： H01L27/0722 , H01L21/761 , H01L21/823878 , H01L21/823892 , H01L21/8249 , H01L27/0928
摘要： A semiconductor integrated circuit including digital circuits and analog circuits integrated over a single substrate includes the substrate including portions where the digital circuits and the analog circuits are to be formed, and a plurality of deep-wells formed to a certain thickness inside the substrate to surround portions where devices of the digital circuits and devices of the analog circuits are to be formed to reduce interference between the devices of the analog circuits and the digital circuits.
摘要翻译：包括集成在单个基板上的数字电路和模拟电路的半导体集成电路包括：基板，包括要形成数字电路和模拟电路的部分;以及在基板内形成一定厚度的多个深阱，要形成数字电路的设备和模拟电路的设备的部分，以减少模拟电路的设备与数字电路之间的干扰。

113. 发明授权

US07868423B2 Optimized device isolation 有权
标题翻译：优化设备隔离
公开(公告)号：US07868423B2
公开(公告)日：2011-01-11
申请号：US12269073
申请日：2008-11-12
申请人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St. Onge , James A. Slinkman
发明人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St. Onge , James A. Slinkman
IPC分类号： H01L21/02
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928
摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.
摘要翻译：用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。隔离MOSFET的n阱连接到深n波段区域。所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

114. 发明授权

US07847616B2 Inverter circuit and balanced input inverter circuit 有权
公开(公告)号：US07847616B2
公开(公告)日：2010-12-07
申请号：US12585511
申请日：2009-09-16
申请人： Yasuhiro Hashimoto
发明人： Yasuhiro Hashimoto
IPC分类号： H03K3/01 , H01L29/94
CPC分类号： H03K19/0013 , H01L27/0629 , H01L27/0928
摘要： A balanced input inverter circuit includes a first P-type MOS transistor including a gate terminal connected to an input, a source terminal connected to a first power source potential, and a drain terminal connected to an output, a first N-type MOS transistor including a gate terminal connected to the input, a drain terminal connected to the output, and a source terminal connected to a second power source potential, a first inverter circuit including an input terminal connected to an inverted input, and an output terminal connected to a back gate terminal of the first N-type MOS transistor, a first diode connected between the first power source potential and a first power source terminal of the first inverter circuit, a second inverter circuit including an input terminal connected to the inverted input, and an output terminal connected to a back gate terminal of the first P-type MOS transistor, and a second diode connected between the second power source potential and a second power source terminal of the second inverter circuit.

115. 发明授权

US07847339B2 Semiconductor integrated circuit devices having conductive patterns that are electrically connected to junction regions 有权
标题翻译：具有电连接到结区域的导电图案的半导体集成电路器件
公开(公告)号：US07847339B2
公开(公告)日：2010-12-07
申请号：US12165827
申请日：2008-07-01
申请人： Bong-Hyun Lee , Jung-Yun Choi
发明人： Bong-Hyun Lee , Jung-Yun Choi
IPC分类号： H01L29/788
CPC分类号： H01L21/74 , H01L21/28123 , H01L21/823892 , H01L27/0928
摘要： A semiconductor integrated circuit device includes a semiconductor substrate; a dummy pattern extending in one direction on the semiconductor substrate; a junction region electrically connecting the dummy pattern to the semiconductor substrate; and a voltage applying unit that is configured to apply a bias voltage to the dummy pattern.
摘要翻译：半导体集成电路器件包括半导体衬底; 在半导体衬底上沿一个方向延伸的虚拟图案; 将虚设图案电连接到半导体衬底的接合区域; 以及电压施加单元，被配置为向所述虚拟图案施加偏置电压。

116. 发明授权

US07692217B2 Matched analog CMOS transistors with extension wells 有权
标题翻译：具有扩展阱的匹配模拟CMOS晶体管
公开(公告)号：US07692217B2
公开(公告)日：2010-04-06
申请号：US11948172
申请日：2007-11-30
申请人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
发明人： Henry Litzmann Edwards , Hisashi Shichijo , Tathagata Chatterjee , Shyh-Horng Yang , Lance Stanford Robertson
IPC分类号： H01L27/148
CPC分类号： H01L21/823892 , H01L21/823814 , H01L27/0928
摘要： One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及集成电路。集成电路包括第一匹配晶体管，包括：第一源极区域，形成在第一漏极阱延伸部内的第一漏极区域和具有横向边缘的第一栅极电极，第一源极区域和第一漏极区域围绕第一源极区域横向设置。集成电路还包括第二匹配晶体管，其包括：第二源极区域，形成在第二漏极阱延伸部内的第二漏极区域和具有横向边缘的第二栅极电极，第二源极区域和第二漏极区域围绕第二源极区域横向设置。模拟电路与第一和第二匹配晶体管相关联，该模拟电路利用第一和第二匹配晶体管的匹配特性来促进模拟功能。还公开了其他装置，方法和系统。

117. 发明授权

US07659188B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07659188B2
公开(公告)日：2010-02-09
申请号：US11398651
申请日：2006-04-06
申请人： Takuji Tanaka
发明人： Takuji Tanaka
IPC分类号： H01L21/00
CPC分类号： H01L21/26513 , H01L21/823892 , H01L27/0928 , H01L29/78
摘要： The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.
摘要翻译：本发明提供一种制造半导体器件的方法，该方法包括在半导体衬底的远离其表面的位置处形成一个可选的杂质区的步骤，并且在上述方法中，多次进行离子注入用于离子注入的掩模图案的端部的位置改变。

118. 发明申请

US20100025816A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100025816A1
公开(公告)日：2010-02-04
申请号：US12458139
申请日：2009-07-01
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Yasutaka Nakashiba
IPC分类号： H01L29/92 , G11C5/14
CPC分类号： H01L21/823878 , H01L21/823892 , H01L27/0733 , H01L27/0928
摘要： A width of a region where each of the N wells is in contact with the buried P well is not more than 2 μm. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.
摘要翻译：每个N个阱与埋置的P阱接触的区域的宽度不大于2μm。接地电压和电源电压分别施加到P阱和N阱。在N阱和P阱之间形成去耦电容。

119. 发明授权

US07645664B1 Layout pattern for deep well region to facilitate routing body-bias voltage 有权
标题翻译：用于深井区域的布局图，以方便路偏偏置电压
公开(公告)号：US07645664B1
公开(公告)日：2010-01-12
申请号：US11449952
申请日：2006-06-08
申请人： Mike Pelham , James B. Burr
发明人： Mike Pelham , James B. Burr
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/0646 , G11C5/146 , H01L21/823493 , H01L21/823892 , H01L23/481 , H01L27/0203 , H01L27/0222 , H01L27/0928 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
摘要翻译：提供并描述了深阱区域的布局图案，以便于在半导体器件中布置体偏置电压。布局图案包括对角子表面网格结构，轴向子表面网格结构，对角子表面条带结构和轴向子表面条带结构。根据几个因素，为半导体器件的区域选择特定的布局图案。

120. 发明授权

US07595558B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07595558B2
公开(公告)日：2009-09-29
申请号：US11706700
申请日：2007-02-15
申请人： Wan Cheul Shin
发明人： Wan Cheul Shin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/823493 , H01L21/761 , H01L21/823481 , H01L27/0921 , H01L27/0928
摘要： A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.
摘要翻译：半导体器件包括形成在半导体衬底的预定区域中的第一阱，形成在第一阱中的预定区域中的第二阱，以及形成在第一阱中的第三阱，第三阱与第二阱间隔开在预定距离处。形成依次布置的半导体衬底，第一阱，第二阱，第一阱和第三阱的多个阱。因此，可以提高击穿电压并且可以减小漏电流。因此，可以防止擦除电压的下降并且减少擦除操作的误差。

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