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111. 发明授权

US09209036B2 Method for controlling the profile of an etched metallic layer 有权
标题翻译：用于控制蚀刻金属层的轮廓的方法
公开(公告)号：US09209036B2
公开(公告)日：2015-12-08
申请号：US14187598
申请日：2014-02-24
申请人： International Business Machines Corporation , STMicroelectronics, Inc.
发明人： Lawrence A. Clevenger , Carl J. Radens , Richard S. Wise , Edem Wornyo , Yiheng Xu , John Zhang
IPC分类号： H01L21/302 , H01L21/308
CPC分类号： H01L29/0661 , H01L21/02071 , H01L21/0337 , H01L21/3085 , H01L21/3086 , H01L21/31138 , H01L21/31144 , H01L21/32139 , H01L29/66621 , H01L29/66795 , H01L51/0525
摘要： An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.
摘要翻译：提供采用Cl 2和N 2的组合的灰化化学品，其从图案化的金属硬掩模层的侧壁除去剩余材料，而不残留物，使得图案化的金属硬掩模层的侧壁是垂直的。图案化的金属硬掩模层的侧壁的垂直分布可以有利地用于减少转印到下层中的图案与形成在金属硬掩模层上的图案之间的蚀刻偏压中的图案因子依赖性。此外，灰化化学可以用于增强在金属材料层的垂直部分中的桁条的去除。

112. 发明授权

US09177820B2 Sub-lithographic semiconductor structures with non-constant pitch 有权
标题翻译：具有非恒定间距的次光刻半导体结构
公开(公告)号：US09177820B2
公开(公告)日：2015-11-03
申请号：US13659318
申请日：2012-10-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Marc A. Bergendahl , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/20 , H01L21/36 , H01L21/308 , H01L21/28
CPC分类号： H01L21/3088 , H01L21/2815 , H01L21/3065 , H01L21/3085 , H01L21/3086
摘要： Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.
摘要翻译：公开了使用双材料侧壁图像转印掩模制造翅片结构以实现亚光刻特征图案化的翅片结构和方法。形成多个翅片的方法包括形成具有第一间距的第一组翅片。该方法还包括形成与第一组翅片相邻的翅片。相邻翅片和第一组翅片的最近的翅片具有比第一节距大的第二节距。第一组翅片和相邻翅片是使用侧壁图像转移过程形成的亚光刻特征。

113. 发明授权

US09159576B2 Method of forming finFET having fins of different height 有权
标题翻译：形成具有不同高度的翅片的finFET的方法
公开(公告)号：US09159576B2
公开(公告)日：2015-10-13
申请号：US13784867
申请日：2013-03-05
申请人： QUALCOMM Incorporated
发明人： Stanley Seungchul Song
IPC分类号： H01L21/308 , H01L29/66 , H01L21/762 , H01L21/32
CPC分类号： H01L21/3085 , H01L21/3065 , H01L21/3081 , H01L21/32 , H01L21/76205 , H01L21/845 , H01L27/0886 , H01L29/66795
摘要： A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer.
摘要翻译：在由衬底形成的绝缘体上硅（SOI）晶片，衬底上的底部氧化物层和底部氧化物层上的活性硅层上进行方法，其中活性硅层具有与底部氧化物相对的表面层。该方法包括在晶片的第一部分处在表面上形成第一掩模，并且离开晶片的第二部分未被屏蔽，在晶片的未屏蔽的第二部分处蚀刻晶片以在有源硅层中形成凹陷，凹陷具有底部，形成基本上填充凹陷的热氧化层，去除第一掩模，以及在晶片的第一和第二部分处形成翅片。

114. 发明授权

US09153456B2 Pattern forming method using block copolymers 有权
标题翻译：使用嵌段共聚物的图案形成方法
公开(公告)号：US09153456B2
公开(公告)日：2015-10-06
申请号：US14100549
申请日：2013-12-09
申请人： Kabushiki Kaisha Toshiba
发明人： Yumi Nakajima , Kentaro Matsunaga
IPC分类号： H01L21/311 , H01L21/308 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/3086 , H01L21/0271 , H01L21/0337 , H01L21/3085
摘要： According to one embodiment, first, on a process object, a hydrophilic guide pattern including a first hole forming pattern having a first hole diameter and a second hole forming pattern having a second hole diameter is formed. Then, above the guide pattern, a frame pattern having a first opening region in a forming region of a plurality of the first hole forming patterns and a second opening region in a forming region of a plurality of the second hole forming patterns is formed. Then, a first solution including a first block copolymer having a hydrophilic polymer chain and a hydrophobic polymer chain is supplied to the first opening region to condense the first block copolymer. The hydrophilic polymer chain is then removed to reduce the diameter of the first hole forming pattern to a third hole diameter that is smaller than the first hole diameter.
摘要翻译：根据一个实施例，首先，在加工对象物上，形成包括具有第一孔径的第一孔形成图案和具有第二孔径的第二孔形成图案的亲水性引导图案。然后，在引导图案之上形成有在多个第一孔形成图案的形成区域中具有第一开口区域和在多个第二孔形成图案的形成区域中的第二开口区域的框架图案。然后，将包含具有亲水性聚合物链和疏水性聚合物链的第一嵌段共聚物的第一溶液供给至第一开口部，使第一嵌段共聚物缩合。然后去除亲水性聚合物链以将第一孔形成图案的直径减小到小于第一孔直径的第三孔直径。

115. 发明授权

US09153455B2 Methods of forming semiconductor device structures, memory cells, and arrays 有权
标题翻译：形成半导体器件结构，存储单元和阵列的方法
公开(公告)号：US09153455B2
公开(公告)日：2015-10-06
申请号：US13921509
申请日：2013-06-19
申请人： Micron Technology, Inc.
发明人： Christopher J. Larsen , David A. Daycock , Kunal Shrotri
IPC分类号： H01L29/788 , H01L21/308 , H01L21/28 , H01L27/115 , H01L29/423
CPC分类号： H01L29/42324 , H01L21/02164 , H01L21/0228 , H01L21/02337 , H01L21/28273 , H01L21/3085 , H01L21/3086 , H01L21/32139 , H01L27/11517 , H01L27/11521 , H01L27/11558 , H01L29/0649 , H01L29/788
摘要： Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
摘要翻译：形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和具有基本对准侧壁的封盖区域和在控制栅极区域下方的电荷结构。

116. 发明申请

US20150255299A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING SELECTIVELY FORMING AND REMOVING FIN STRUCTURES 有权
标题翻译：整合电路的方法，包括选择性形成和去除晶体结构
公开(公告)号：US20150255299A1
公开(公告)日：2015-09-10
申请号：US14196931
申请日：2014-03-04
申请人： GLOBALFOUNDRIES, Inc.
发明人： Jason Richard Cantone , Linus Jang , Jin Cho , Ryan Ryoung-Han Kim
IPC分类号： H01L21/308
CPC分类号： H01L21/3086 , H01L21/3085 , H01L21/823431 , H01L21/845
摘要： Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.
摘要翻译：提供了制造集成电路的方法。在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。

117. 发明申请

US20150243547A1 SEMICONDUCTOR LINE FEATURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体线特征及其制造方法
公开(公告)号：US20150243547A1
公开(公告)日：2015-08-27
申请号：US14192439
申请日：2014-02-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： WEN-HAN FANG , PO-CHI WU
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76232 , H01J37/321 , H01L21/3065 , H01L21/3081 , H01L21/3085 , H01L21/31116 , H01L29/78
摘要： Some embodiments of the present disclosure provide a semiconductor structure with a reduced line feature. The semiconductor structure includes a substrate, a first active region in the substrate and having a first sidewall, a second active region in the substrate and having a second sidewall, an isolation region contacting the first sidewall and the second sidewall. The above-mentioned semiconductor structure possesses a width of a top surface of the isolation region less than 50 nm and a width of a bottom surface of the isolation region more than 20 nm. Some embodiments provide a method for controlling a semiconductor line feature in a wafer, including patterning a hard mask exposing a line feature with a line width narrower than 50 nm on a wafer, forming a trench on the wafer correlated to the line feature by performing a plasma dry etch over the wafer, and filling the trench with isolation materials.
摘要翻译：本公开的一些实施例提供具有减少的线特征的半导体结构。半导体结构包括衬底，衬底中的第一有源区，并具有第一侧壁，衬底中的第二有源区，并具有第二侧壁，接触第一侧壁和第二侧壁的隔离区。上述半导体结构具有小于50nm的隔离区的顶表面的宽度和大于20nm的隔离区的底表面的宽度。一些实施例提供了一种用于控制晶片中的半导体线特征的方法，包括对在晶片上露出具有窄于50nm的线宽的线特征的硬掩模进行图案化，在晶片上形成与线特征相关的沟槽，通过执行在晶片上进行等离子体干蚀刻，并用隔离材料填充沟槽。

118. 发明申请

US20150236131A1 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE AND METHOD FOR FORMING THE SAME 有权
标题翻译： FIN场效应晶体管（FINFET）器件及其形成方法
公开(公告)号：US20150236131A1
公开(公告)日：2015-08-20
申请号：US14180932
申请日：2014-02-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd
发明人： Che-Cheng CHANG , Yung-Jung CHANG
IPC分类号： H01L29/66 , H01L29/40 , H01L21/28 , H01L27/088
CPC分类号： H01L29/66795 , H01L21/30604 , H01L21/3085 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/66545 , H01L29/785
摘要： Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a substrate and a first fin structure extending above the substrate. The FinFET also includes a first transistor formed on the first fin structure. The first transistor includes a first gate dielectric layer conformally formed on the first fin structure and a first gate electrode formed on the first gate dielectric layer. The FinFET further includes an inter-layer dielectric (ILD) structure formed adjacent to the first transistor. The first gate electrode is in direct contact with a sidewall of the ILD structure.
摘要翻译：提供了用于形成鳍状场效应晶体管（FinFET）器件结构的实施例。 FinFET器件结构包括衬底和在衬底上延伸的第一鳍结构。 FinFET还包括形成在第一鳍结构上的第一晶体管。第一晶体管包括保形地形成在第一鳍结构上的第一栅介质层和形成在第一栅介质层上的第一栅电极。 FinFET还包括与第一晶体管相邻形成的层间电介质（ILD）结构。第一栅电极与ILD结构的侧壁直接接触。

119. 发明申请

US20150235895A1 Spacer Enabled Active Isolation for an Integrated Circuit Device 有权
标题翻译：用于集成电路器件的隔板启用主动隔离
公开(公告)号：US20150235895A1
公开(公告)日：2015-08-20
申请号：US14184177
申请日：2014-02-19
申请人： Microchip Technology Incorporated
发明人： Paul Fest
IPC分类号： H01L21/762 , H01L21/308 , H01L29/06
CPC分类号： H01L21/76224 , H01L21/308 , H01L21/3081 , H01L21/3085 , H01L21/3086 , H01L21/3088 , H01L21/31 , H01L21/31053 , H01L21/76
摘要： A method for forming an active isolation structure in a semiconductor integrated circuit die is disclosed. A first hard mask layer is deposited over a semiconductor substrate. Portions of the first hard mask layer are removed to form at least one trench. A spacer layer is deposited over the first hard mask and extends into each trench to cover exposed portions of the semiconductor substrate surface in each trench. Portions of the spacer layer are removed such that remaining portions define spacer layer walls covering the side walls of each trench. A second hard mask layer is deposited and extends into each trench between opposing spacer layer walls. The spacer layer walls are removed such that remaining portions of the first and second hard mask layers define a mask pattern, which is then transferred to the substrate to form openings in the substrate, which are filled with an isolation material.
摘要翻译：公开了一种在半导体集成电路管芯中形成有源隔离结构的方法。第一硬掩模层沉积在半导体衬底上。去除第一硬掩模层的部分以形成至少一个沟槽。间隔层沉积在第一硬掩模上并延伸到每个沟槽中以覆盖每个沟槽中的半导体衬底表面的暴露部分。去除间隔层的部分，使得剩余的部分限定覆盖每个沟槽的侧壁的间隔层壁。第二硬掩模层被沉积并延伸到相对间隔层壁之间的每个沟槽中。去除间隔层壁，使得第一和第二硬掩模层的剩余部分限定掩模图案，然后将掩模图案转移到衬底中，以在衬底中形成填充有隔离材料的开口。

120. 发明申请

US20150228623A1 STAIRCASE-SHAPED CONNECTION STRUCTURES OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME 有权
标题翻译：三维半导体器件的平面形状连接结构及其形成方法
公开(公告)号：US20150228623A1
公开(公告)日：2015-08-13
申请号：US14520751
申请日：2014-10-22
申请人： JUNG-IK OH , Daehyun Jang , Ha-Na Kim , Kyoungsub Shin
发明人： JUNG-IK OH , Daehyun Jang , Ha-Na Kim , Kyoungsub Shin
IPC分类号： H01L25/065 , H01L27/115 , H01L25/00 , H01L45/00
CPC分类号： H01L21/0274 , H01L21/30604 , H01L21/3085 , H01L25/0657 , H01L25/50 , H01L27/11521 , H01L27/11556 , H01L27/11575 , H01L27/11582 , H01L27/2481 , H01L45/122 , H01L45/1253 , H01L2924/0002 , H01L2924/00
摘要： Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
摘要翻译：提供了三维半导体器件的阶梯状连接结构。该装置包括在基板上的电极结构，电极结构包括上层阶段区域，下层阶梯区域和它们之间的缓冲区域。电极结构包括依次堆叠在基板上的水平电极，水平电极包括构成上下阶梯区域中的每一个的阶梯结构的多个焊盘区域，并且缓冲区域的宽度大于垫区域。

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