专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

111. 发明授权

US5973960A Nonvolatile semiconductor memory device capable of storing analog or many-valued data at high speed and with a high degree of accuracy 失效
标题翻译：非易失性半导体存储器件能够以高速和高准确度存储模拟或多值数据
公开(公告)号：US5973960A
公开(公告)日：1999-10-26
申请号：US930373
申请日：1998-02-09
申请人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
发明人： Tadashi Shibata , Tadahiro Ohmi , Yuichiro Yamashita
IPC分类号： G11C11/56 , G11C16/04 , G11C27/00 , G11C14/00
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0458 , G11C27/005 , G11C2211/5612 , G11C2211/5613
摘要： A nonvolatile semiconductor memory which is capable of a high degree of integration and can conduct the writing of analog data at high speed and with a high degree of accuracy.The memory device comprises two or more semiconductor devices comprising a first MOS transistor having a first floating gate which is electrically insulated, a first electrode which is capacitively coupled with the first floating gate, a second electrode provided with the first floating gate via a tunnel junction, and a third electrode connected to the second electrode via a switch; the present invention is further provided with a fourth electrode connected commonly with the third electrodes of the semiconductor devices, a fifth electrode connected commonly with the source electrodes of the first MOS transistors, a sixth electrode which is capacitively coupled with the fourth electrode, and a seventh electrode which is connected with the fourth electrode via a switch.
摘要翻译： PCT No.PCT / JP96 / 00884 Sec。 371日期：1998年2月9日 102（e）1998年2月9日PCT PCT 1996年4月1日PCT公布。公开号WO96 / 30948 日期：1996年10月3日是一种能够高集成度并且可以以高速度和高精度地进行模拟数据写入的非易失性半导体存储器。存储器件包括两个或更多个半导体器件，其包括具有电绝缘的第一浮栅的第一MOS晶体管，与第一浮置栅极电容耦合的第一电极，经由隧道结设置有第一浮置栅极的第二电极和通过开关连接到第二电极的第三电极; 本发明还提供有与半导体器件的第三电极共同连接的第四电极，与第一MOS晶体管的源电极共同连接的第五电极，与第四电极电容耦合的第六电极，以及第七电极，其经由开关与第四电极连接。

112. 发明授权

US5963824A Method of making a semiconductor device with adjustable threshold voltage 失效
标题翻译：制造具有可调阈值电压的半导体器件的方法
公开(公告)号：US5963824A
公开(公告)日：1999-10-05
申请号：US891422
申请日：1997-07-09
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： G11C11/56 , G11C16/04 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L21/3205
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5671 , G11C16/0458 , H01L29/4983 , H01L29/66545 , H01L29/66628 , H01L29/66825 , H01L29/78 , H01L29/7887 , G11C2211/5612 , H01L29/42376
摘要： The present invention provides a method of making a semiconductor device with a channel length of approximately 0.05 microns. A method of producing a semiconductor device according to the present invention includes a control gate, a first floating gate located in proximity to the control gate, and a second floating gate located in proximity to the control gate. The present invention allows the threshold voltage of the device to be adjusted to various levels. Additionally, the device according to the present invention can be used as a very effective nonvolatile memory device.
摘要翻译：本发明提供一种制造具有大约0.05微米的通道长度的半导体器件的方法。根据本发明的制造半导体器件的方法包括控制栅极，位于控制栅极附近的第一浮动栅极和位于控制栅极附近的第二浮置栅极。本发明允许将装置的阈值电压调节到各种水平。此外，根据本发明的装置可以用作非常有效的非易失性存储装置。

113. 发明授权

US5923978A Nonvolatile semiconductor memory and methods for manufacturing and using the same 失效
标题翻译：非易失性半导体存储器及其制造和使用方法
公开(公告)号：US5923978A
公开(公告)日：1999-07-13
申请号：US933763
申请日：1997-09-23
申请人： Yosiaki Hisamune
发明人： Yosiaki Hisamune
IPC分类号： G11C17/00 , G11C11/56 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C11/5621 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L29/66825 , H01L29/7887 , G11C2211/5612
摘要： A nonvolatile semiconductor memory is composed of a number of multi-bit memory cells, each including a first floating gate and a second floating gate formed, side by side, and insulated from each other, on a first gate insulator film formed on a channel region defined between a source region and a drain region, a second gate insulator film formed to cover a surface of each of the floating gates, and a control gate formed on the second gate insulator film. The first floating gate is positioned above a source side of the channel region, and the second floating gate is positioned above a drain side of the channel region. At least the first floating gate is formed of a side wall polysilicon having a gate length remarkably smaller than that of the second floating gate or the control gate. Accordingly, the resulting channel length of the memory cell is remarkably reduced, with the result that the occupying area of each memory cell and the occupying area of a necessary peripheral circuit can be reduced.
摘要翻译：非易失性半导体存储器由多个多位存储单元组成，每个多位存储单元包括并排形成并彼此绝缘的第一浮置栅极和第二浮置栅极，形成在沟道区域上的第一栅极绝缘膜上限定在源极区域和漏极区域之间，形成为覆盖每个浮置栅极的表面的第二栅极绝缘膜，以及形成在第二栅极绝缘膜上的控制栅极。第一浮栅位于沟道区的源极侧上方，第二浮栅位于沟道区的漏极侧的上方。至少第一浮栅由栅极长度显着小于第二浮栅或控制栅的栅极长度的侧壁多晶硅形成。因此，存储单元的结果通道长度显着降低，从而可以减少每个存储单元的占用面积和所需外围电路的占用面积。

114. 发明授权

US5898197A Non-volatile semiconductor memory devices 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5898197A
公开(公告)日：1999-04-27
申请号：US870122
申请日：1997-06-03
申请人： Hideaki Fujiwara
发明人： Hideaki Fujiwara
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L29/42324 , H01L29/66825 , H01L29/7885 , H01L29/7887 , G11C2211/5612
摘要： A non-volatile semiconductor memory device accurately stores multivalued data with reduced damage to an insulating layer. The non-volatile semiconductor memory device includes a floating gate electrode configured to be divided into at least two portions. The first portion is employed for accumulating carriers migrating from at least one control gate electrode through a gate insulating layer to the floating gate electrode.
摘要翻译：非易失性半导体存储器件将绝对层损伤降低的多值数据精确地存储。非易失性半导体存储器件包括被构造为分成至少两部分的浮栅电极。第一部分用于累积从至少一个控制栅极迁移通过栅极绝缘层到载体栅电极的载流子。

115. 发明授权

US5812449A Flash EEPROM cell, method of manufacturing the same, method of programming and method of reading the same 失效
标题翻译：闪存EEPROM单元，其制造方法，编程方法及其读取方法
公开(公告)号：US5812449A
公开(公告)日：1998-09-22
申请号：US644211
申请日：1996-05-10
申请人： Bok Nam Song
发明人： Bok Nam Song
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/04 , G11C16/10 , H01L21/28 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0458 , G11C16/10 , H01L21/28273 , H01L29/7887 , G11C2211/5612
摘要： The present invention relates to a flash EEPROM cell, method of manufacturing the same, and method of programming and reading the same and, more particularly, to a flash EEPROM cell constructed in such a way that two floating gates are formed on top of a channel region to implement a memory cell to, and from, which 4-numeration information can be programmed and read out, and an output of 4-numeration information is obtained depending on the programming or erasing of each of the two floating gates.
摘要翻译：闪存EEPROM单元及其制造方法技术领域本发明涉及一种快闪EEPROM单元及其制造方法，以及编程和读取闪存EEPROM单元的方法，更具体地说，涉及一种快闪EEPROM单元，其构造为使得两个浮栅形成在通道顶部区域以实现可编程和读出4个编号信息的存储单元，并且根据两个浮动栅极中的每一个的编程或擦除来获得4数字信息的输出。

116. 发明授权

US5757044A Electrically erasable and programmable read only memory cell with split floating gate for preventing cell from over-erase 失效
标题翻译：电可擦除可编程只读存储单元，具有分离浮动栅极，可防止电池过度擦除
公开(公告)号：US5757044A
公开(公告)日：1998-05-26
申请号：US548523
申请日：1995-10-26
申请人： Taishi Kubota
发明人： Taishi Kubota
IPC分类号： H01L21/8247 , G11C11/56 , G11C16/04 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/4232 , G11C11/5621 , G11C16/0458 , H01L29/7887 , G11C2211/5612
摘要： A floating gate type field effect transistor has a plurality of floating gate sub-electrodes on a lower gate oxide layer electrically isolated from one another; even if one of the floating gate sub-electrodes changes a part of a channel region thereunder to depletion state due to an over-erase, the over-erase does not affect the function of the floating gate type field effect transistor, because another sub-electrode transfers and cuts off channel current depending upon the amount of electrons accumulated therein.
摘要翻译：浮栅型场效应晶体管在彼此电隔离的下栅极氧化物层上具有多个浮置栅极子电极; 即使其中一个浮置栅极子电极由于过度擦除将其中的沟道区域的一部分改变为耗尽状态，因此，过擦除不会影响浮置栅极型场效应晶体管的功能，电极根据其中积累的电子的量转移并切断通道电流。

117. 发明授权

US5753950A Non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture and programming/erasing/reading method for the same 失效
标题翻译：具有通过双层浮栅结构应用于多位数据的单元的非易失性存储器以及用于其的编程/擦除/读取方法
公开(公告)号：US5753950A
公开(公告)日：1998-05-19
申请号：US630184
申请日：1996-04-10
申请人： Toshiaki Kojima
发明人： Toshiaki Kojima
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , G11C16/0475 , H01L29/7887 , G11C2211/5612 , H01L27/115
摘要： An object of the present invention is to contribute to increase of storage capacity of a memory and to cope with an nonlinear parasitic resistance. The non-volatile memory have a cell applying to multi-bit data by means of a double layered floating gate architecture. The cell comprises: heavily doped layers (drains 3.sub.0 -3.sub.2 and source 2) being formed separated from each other along an arrangement direction L in a semiconductor substrate; a first floating gate 4A being disposed along a direction orthogonal to the direction L between the drains and source above the semiconductor substrate; second floating gates 4B.sub.1, 4B.sub.2 which respectively extend across the first floating gate above the first floating gate and lie along the direction L, close to the drain; program gates 6.sub.1, 6.sub.2 disposed correspondingly to one of the second floating gates; and a control gate 5 extending across the gate 4A above the gate 4A and being disposed along the direction L, close to the source.Since the second floating gates individually store carriers corresponding to a data bit and the first floating gate determines a threshold voltage in accordance with a sum amount of carriers stored in all of the second floating gates, two or more bits of data can be saved per one storage cell. It is possible to avoid influence of nonlinear parasitic resistance because a transistor formed by the first floating gate and the control gate is used exclusively for reading.
摘要翻译：本发明的目的是有助于增加存储器的存储容量并且应对非线性寄生电阻。非易失性存储器具有通过双层浮栅结构应用于多位数据的单元。电池包括：在半导体衬底中沿着布置方向L彼此分离形成的重掺杂层（漏极30-32和源极2）第一浮栅4A沿着与半导体基板上方的漏极和源极之间的方向L正交的方向设置; 第二浮栅4B1,4B2分别延伸穿过第一浮动栅极上方的第一浮动栅极并且沿着方向L位于靠近漏极的位置; 对应于第二浮动栅极之一设置的编程门61,62; 以及控制门5，其跨过门4A上方的栅极4A延伸，并且沿着方向L设置，靠近源极。由于第二浮动门单独存储对应于数据位的载波，并且第一浮动栅极根据存储在所有第二浮动栅极中的载波的总和量来确定阈值电压，因此可以每一个存储两个或更多位的数据存储单元。由于由第一浮栅和控制栅形成的晶体管专门用于读取，所以可以避免非线性寄生电阻的影响。

118. 发明授权

US5674768A Method of making flash EEPROM cell having first and second floating gates 失效
标题翻译：制造具有第一和第二浮动栅极的快闪EEPROM单元的方法
公开(公告)号：US5674768A
公开(公告)日：1997-10-07
申请号：US620894
申请日：1996-03-22
申请人： Sang Hwan Chang , Sung Oh Han
发明人： Sang Hwan Chang , Sung Oh Han
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L27/115 , H01L27/11517 , H01L29/7887 , G11C2211/5612
摘要： This invention relates to a Flash EEPROM (Electrically erasable programmable Read-Only Memory) cell and manufacturing methods thereof, especially which is capable of three different output levels by the variation of effective channel length depending on whether either or all of two floating gates are programmed or erased and the combination of bias, in which two floating gates are formed on a channel region.
摘要翻译：本发明涉及一种闪存EEPROM（电可擦除可编程只读存储器）单元及其制造方法，特别是根据两个浮动栅极中的一个或全部是否被编程，能够通过有效沟道长度的变化而具有三个不同的输出电平或擦除，以及偏置的组合，其中在沟道区上形成两个浮置栅极。

119. 发明授权

US5424979A Non-volatile memory cell 失效
标题翻译：非易失性存储单元
公开(公告)号：US5424979A
公开(公告)日：1995-06-13
申请号：US245253
申请日：1994-05-17
申请人： Tomoyuki Morii
发明人： Tomoyuki Morii
IPC分类号： G11C11/56 , G11C16/04 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/78
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L21/2815 , H01L29/42324 , H01L29/66825 , H01L29/7883 , G11C2211/5612 , H01L27/115
摘要： A non-volatile memory cell according to the present invention includes: a semiconductor layer of a first conductivity type having an upper portion; a pair of impurity diffusion regions of a second conductivity type provided in the upper portion of the semiconductor layer, facing each other at a certain distance; a channel region provided between the pair of impurity diffusion regions in the upper portion of the semiconductor layer; a gate insulating film provided on the upper portion of the semiconductor layer, having thin portions covering at least part of the pair of impurity diffusion regions and a thick portion covering the channel region; floating gate electrodes provided on the thin portions of the gate insulating film; a control gate electrode provided on the thick portion of the gate insulating film and electrically insulated from the floating gate electrodes; and an insulating film provided between the control gate electrode and the floating gate electrodes, capacity-coupling the control gate electrode with the floating gate electrodes, wherein, during writing data, part of electric carriers in the impurity diffusion regions are injected into the floating gate electrodes through the thin portions of the gate insulating film so as to form a Fowler-Nordheim current, depending upon a voltage to be applied to the control gate electrode, whereby electric resistance of the impurity diffusion regions is changed.
摘要翻译：根据本发明的非易失性存储单元包括：具有上部的第一导电类型的半导体层; 一对第二导电类型的杂质扩散区域设置在半导体层的上部，以一定距离彼此面对; 沟道区，设置在所述半导体层的上部的所述一对杂质扩散区之间; 设置在所述半导体层的上部的栅绝缘膜，具有覆盖所述一对杂质扩散区域的至少一部分的薄部分和覆盖所述沟道区域的厚部; 设置在栅绝缘膜的薄部上的浮栅电极; 控制栅电极，其设置在所述栅极绝缘膜的厚部并与所述浮栅电极电绝缘; 以及设置在所述控制栅电极和所述浮栅之间的绝缘膜，使所述控制栅电极与所述浮栅电容耦合，其中，在写数据期间，所述杂质扩散区中的一部分电载体注入到所述浮栅电极通过栅极绝缘膜的薄部分，以形成Fowler-Nordheim电流，这取决于施加到控制栅电极的电压，由此改变杂质扩散区域的电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式