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111. 发明申请

US20160313993A1 APPARATUS AND METHOD OF EXECUTION UNIT FOR CALCULATING MULTIPLE ROUNDS OF A SKEIN HASHING ALGORITHM 审中-公开
标题翻译：用于计算多重环绕滑移算法的执行单元的装置和方法
公开(公告)号：US20160313993A1
公开(公告)日：2016-10-27
申请号：US15203610
申请日：2016-07-06
申请人： Intel Corporation
发明人： GILBERT M. WOLRICH , KIRK S. YAP , JAMES D. GUILFORD , ERDINC OZTURK , VINODH GOPAL , WAJDI K. FEGHALI , SEAN M. GULLEY , MARTIN G. DIXON
IPC分类号： G06F9/30 , H04L9/06 , G06F9/38
CPC分类号： G06F9/30029 , G06F9/30007 , G06F9/30018 , G06F9/30036 , G06F9/3885 , G06F9/3895 , H04L9/0643
摘要： An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.
摘要翻译：描述了包括指令流水线内的执行单元的装置。执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入接收第二个四字; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

112. 发明申请

US20160308676A1 RSA ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译： RSA算法加速处理器，方法，系统和指令
公开(公告)号：US20160308676A1
公开(公告)日：2016-10-20
申请号：US15102637
申请日：2013-12-28
申请人： Yang LU , Xiangzheng SUN , Nan Stan QIAO , INTEL CORPORATION
发明人： Yang Lu , Xiangzheng Sun , Nan Qiao
IPC分类号： H04L9/30 , G06F9/30 , G06F7/72
CPC分类号： H04L9/302 , G06F7/722 , G06F7/723 , G06F9/30007 , G06F9/3017 , G09C1/00
摘要： A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a second 64-bit source operand having a second 64-bit value, indicates a third 64-bit source operand having a third 64-bit value, and indicates a fourth 64-bit source operand having a fourth 64-bit value. An execution unit is coupled with the decode unit. The execution unit is operable, in response to the instruction, to store a result. The result includes the first 64-bit value multiplied by the second 64-bit value added to the third 64-bit value added to the fourth 64-bit value. The execution unit may store a 64-bit least significant half of the result in a first 64-bit destination operand indicated by the instruction, and store a 64-bit most significant half of the result in a second 64-bit destination operand indicated by the instruction.
摘要翻译：处理器包括解码指令译码单元。该指令指示具有第一64位值的第一64位源操作数，指示具有第二64位值的第二64位源操作数，指示具有第三64位值的第三64位源操作数，并且指示具有第四个64位值的第四个64位源操作数。执行单元与解码单元耦合。执行单元响应于该指令可操作以存储结果。结果包括第一个64位值乘以加到第四个64位值的第三个64位值的第二个64位值。执行单元可以将结果的64位最不重要的一半存储在由指令指示的第一个64位目标操作数中，并将结果的64位最高有效的一半存储在第二个64位目标操作数中，指示。

113. 发明授权

US09424000B2 Instruction for performing a pseudorandom number seed operation 有权
公开(公告)号：US09424000B2
公开(公告)日：2016-08-23
申请号：US14550979
申请日：2014-11-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dan F. Greiner , Bernd Nerz , Tamas Visegrady
IPC分类号： G06F7/58 , G06F9/30 , G06F9/38 , G06F9/455
CPC分类号： H04L9/0668 , G06F7/582 , G06F9/30007 , G06F9/3001 , G06F9/3895 , G06F9/455
摘要： A machine instruction is provided that includes an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation, and a register field to be used to identify a register, the register to specify a location in memory of a second operand to be used. The machine instruction is executed, and execution includes obtaining a modifier field of a register associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number seed operation, which includes obtaining seed material based on information stored in the second operand; using a 512 bit secure hash technique and the seed material to provide one or more seed values; and storing the one or more seed values in a parameter block.

114. 发明授权

US09411532B2 Methods and systems for transferring data between a processing device and external devices 有权
标题翻译：用于在处理设备和外部设备之间传送数据的方法和系统
公开(公告)号：US09411532B2
公开(公告)日：2016-08-09
申请号：US14728422
申请日：2015-06-02
申请人： PACT XPP TECHNOLOGIES AG
发明人： Martin Vorbach , Volker Baumgarte , Frank May , Armin Nuckel
IPC分类号： G06F3/00 , G06F5/00 , G06F13/36 , G06F3/06 , G06F13/10 , G06F13/38 , G06F9/45
CPC分类号： G06F9/30007 , G06F3/0608 , G06F3/061 , G06F3/0647 , G06F3/0673 , G06F3/0683 , G06F8/457 , G06F13/102 , G06F13/385
摘要： An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.
摘要翻译：阵列数据处理器采用多个地址生成器来在数据处理器和外部设备的组之间进行通信。在另一方面，数据处理器采用具有多个指针的缓冲器系统，其允许在传输失败时从缓冲器重发数据。

115. 发明申请

US20160204938A1 METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD 审中-公开
公开(公告)号：US20160204938A1
公开(公告)日：2016-07-14
申请号：US14881121
申请日：2015-10-12
申请人： Intel Corporation
发明人： Michael E. Kounavis , Shay Gueron , Ram Krishnamurthy , Sanu K. Mathew
IPC分类号： H04L9/30 , H04L9/06
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.

116. 发明申请

US20160119130A1 FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) 审中-公开
公开(公告)号：US20160119130A1
公开(公告)日：2016-04-28
申请号：US14984673
申请日：2015-12-30
申请人： Intel Corporation
发明人： Gueron Shay , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
IPC分类号： H04L9/06 , G06F9/38
CPC分类号： H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
摘要： A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

117. 发明申请

US20160119123A1 FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES) 审中-公开
公开(公告)号：US20160119123A1
公开(公告)日：2016-04-28
申请号：US14984588
申请日：2015-12-30
申请人： Intel Corporation
发明人： Gueron Shay , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
IPC分类号： H04L9/06 , G06F9/30 , G06F12/08
CPC分类号： H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
摘要： A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.

118. 发明授权

US09325498B2 Performing AES encryption or decryption in multiple modes with a single instruction 有权
公开(公告)号：US09325498B2
公开(公告)日：2016-04-26
申请号：US13790748
申请日：2013-03-08
申请人： Intel Corporation
发明人： Martin Dixon , Srinivas Chennupaty , Shay Gueron
IPC分类号： G06F21/00 , H04L9/28 , H04L9/06
CPC分类号： H04L9/0631 , G06F9/30007 , H04L9/0637 , H04L9/28 , H04L2209/12
摘要： A machine-readable medium may have stored thereon an instruction, which when executed by a machine causes the machine to perform a method. The method may include combining a first operand of the instruction and a second operand of the instruction to produce a result. The result may be encrypted using a key in accordance with an Advanced Encryption Standard (AES) algorithm to produce an encrypted result. The method may also include placing the encrypted result in a location of the first operand of the instruction.

119. 发明授权

US09317719B2 SM3 hash algorithm acceleration processors, methods, systems, and instructions 有权
标题翻译： SM3散列算法加速处理器，方法，系统和指令
公开(公告)号：US09317719B2
公开(公告)日：2016-04-19
申请号：US14477552
申请日：2014-09-04
申请人： Intel Corporation
发明人： Shay Gueron , Vlad Krasnov
IPC分类号： H04L9/06 , G06F21/72 , G06F9/30
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/3895 , G09C1/00 , H04L2209/125
摘要： A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.
摘要翻译：处理器包括解码单元，用于解码SM3两轮状态字更新指令。该指令是指示一个或多个源打包数据操作数。源压缩数据操作数将具有与SM3哈希算法的一个圆（j）相对应的8个32位状态字Aj，Bj，Cj，Dj，Ej，Fj，Gj和Hj。源压缩数据操作数还具有足以评估两轮SM3哈希算法的一组消息。与解码单元耦合的执行单元可响应于该指令而在一个或多个目的地存储位置中存储一个或多个结果打包数据操作数。结果打包数据操作数将具有至少四个二轮更新的32位状态字Aj + 2，Bj + 2，Ej + 2和Fj + 2，它们对应于一个圆（j + 2）的SM3哈希算法。

120. 发明申请

US20160092241A1 SINGLE INSTRUCTION ARRAY INDEX COMPUTATION 有权
标题翻译：单指令阵列指数计算
公开(公告)号：US20160092241A1
公开(公告)日：2016-03-31
申请号：US14500171
申请日：2014-09-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael K. Gschwind
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/30007 , G06F9/3001 , G06F9/30032 , G06F9/30134 , G06F9/345 , G06F9/355 , G06F9/3552 , G06F9/3555 , G06F9/3557 , G06F12/0223 , G06F15/8007
摘要： Embodiments are directed to a method of adjusting an index, wherein the index identifies a location of an element within an array. The method includes executing, by a computer, a single instruction that adjusts a first parameter of the index to match a parameter of an array address. The single instruction further adjusts a second parameter of the index to match a parameter of the array element. The adjustment of the first parameter includes a sign extension.
摘要翻译：实施例涉及一种调整索引的方法，其中索引标识阵列内的元素的位置。该方法包括由计算机执行调整索引的第一参数以匹配阵列地址的参数的单个指令。单个指令进一步调整索引的第二个参数以匹配数组元素的参数。第一个参数的调整包括一个符号扩展。

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