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    • 113. 发明申请
    • STORAGE APPARATUS AND METHOD FOR AUTONOMOUS SPACE COMPACTION
    • 储存装置和自动空间压缩方法
    • US20160350007A1
    • 2016-12-01
    • US14863438
    • 2015-09-23
    • Inseok Stephen CHOIYang Seok KISheng QIU
    • Inseok Stephen CHOIYang Seok KISheng QIU
    • G06F3/06G06F12/02
    • G06F3/0608G06F3/0638G06F3/0683G06F12/0238G06F2212/1044G06F2212/163G06F2212/7205
    • Embodiments of the inventive concept improve performance, energy efficiency, and capacity of storage solutions, for example, by reducing the data movement between the CPU and the storage device and increasing the available capacity of the underlying storage devices via in-storage support for data compaction. Embodiments include a storage apparatus and method for autonomous in-storage space compaction initiated by a host-side command and according to metadata specified by a host. A space compact engine can function as an independent module or logic section within a storage device, which can migrate data within the storage device, thereby freeing up capacity and making preexisting data more compact. The space compact engine can cause self compact operations, self compact and trim operations, move and compact operations, and/or merge and compact operations. The space compact engine can notify the host of the completion of the operations.
    • 本发明概念的实施例通过减少CPU和存储设备之间的数据移动来提高存储解决方案的性能,能量效率和容量,并通过用于数据压缩的存储器支持来增加底层存储设备的可用容量 。 实施例包括用于由主机侧命令发起的自主存储空间压缩并根据由主机指定的元数据的存储装置和方法。 空间紧凑型引擎可以用作存储设备内的独立模块或逻辑部分,可以迁移存储设备内的数据,从而释放容量并使预先存在的数据更加紧凑。 空间紧凑型发动机可以实现自动紧凑的操作,自动紧凑和调整操作,移动和紧凑的操作,和/或合并和紧凑的操作。 空间紧凑型引擎可以通知主机完成操作。
    • 115. 发明申请
    • Hierarchical FTL Mapping Optimized for Workload
    • 针对工作负载优化的分层FTL映射
    • US20160342509A1
    • 2016-11-24
    • US14720470
    • 2015-05-22
    • SanDisk Enterprise IP LLC
    • Dharani KotteAkshay MathurSatish B. VasudevaSumant K. Patro
    • G06F12/02G06F12/06
    • G06F12/0246G06F12/0638G06F2212/205G06F2212/7201G06F2212/7205
    • In a memory system having non-volatile memory and volatile memory, write data are stored in a write-coalescing buffer in the volatile memory until the write data is written to non-volatile memory. First and second level address mapping tables are stored in the volatile memory and corresponding first and second level address mapping tables are stored in the non-volatile memory, and furthermore the second level address mapping table in the volatile memory contains entries corresponding to only a subset of the entries in the second level address mapping table in the non-volatile memory. The first address-mapping table in volatile memory includes entries storing pointers to entries in the second address-mapping table in volatile memory, entries storing pointers to locations in the write-coalescing buffer, and entries storing pointers to locations in the non-volatile memory that store data.
    • 在具有非易失性存储器和易失性存储器的存储器系统中,将写入数据存储在易失性存储器中的写合并缓冲器中,直到写入数据被写入非易失性存储器。 第一级地址映射表和第二级地址映射表存储在易失性存储器中,并且对应的第一级和第二级地址映射表存储在非易失性存储器中,此外,易失性存储器中的第二级地址映射表包含仅对应于子集的条目 的非易失性存储器中的第二级地址映射表中的条目。 易失性存储器中的第一地址映射表包括存储指向在易失性存储器中的第二地址映射表中的条目的条目的条目,存储指向写 - 合并缓冲器中的位置的条目,以及存储指向非易失性存储器中的位置的条目的条目 存储数据。
    • 116. 发明申请
    • MEMORY ERASING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS
    • 存储器擦除方法,存储器控制器和存储器存储器
    • US20160342355A1
    • 2016-11-24
    • US15229125
    • 2016-08-05
    • PHISON ELECTRONICS CORP.
    • Wei-Chen Teo
    • G06F3/06
    • G06F3/0625G06F3/0652G06F3/0659G06F3/0688G06F12/0246G06F2212/7205
    • A memory erasing method and a memory controller and a memory storage apparatus using the same are provided. The method comprising establishing a link list according to a plurality of physical blocks of a spare area, and storing the link list into the rewritable non-volatile memory module, wherein the physical blocks of the spare area are recorded in the link list according to an arrangement order; and during every power on of the memory storage apparatus, selecting a plurality of third physical blocks among the physical blocks in the spare area according to the link list and a predetermined number, and respectively executing an erase command on the third physical blocks, wherein the third physical blocks are arranged at a beginning of the link list, and the number of the third physical blocks is the predetermined number.
    • 提供了一种存储器擦除方法和存储器控制器以及使用其的存储器存储装置。 该方法包括根据备用区域的多个物理块建立链路列表,并将链路列表存储到可重写非易失性存储器模块中,其中备用区域的物理块根据 安排顺序 并且在所述存储器装置的每次通电期间,根据所述链路列表和预定数量,在所述备用区域中的所述物理块中选择多个第三物理块,并且分别在所述第三物理块上执行擦除命令,其中, 第三物理块被布置在链接列表的开始处,并且第三物理块的数量是预定数量。
    • 120. 发明申请
    • MEMORY SYSTEM EXECUTING GARBAGE COLLECTION
    • 记忆系统执行GARBAGE系列
    • US20160321171A1
    • 2016-11-03
    • US14848844
    • 2015-09-09
    • Kabushiki Kaisha Toshiba
    • Shinichi Kanno
    • G06F12/02G06F3/06
    • G06F12/0253G06F3/0619G06F3/0655G06F3/0688G06F12/0246G06F2212/1016G06F2212/7201G06F2212/7205
    • According to one embodiment, a memory system includes a nonvolatile memory, detection unit, management unit, selection unit, and garbage collection unit. The nonvolatile memory includes memory areas divided into units of execution of garbage collection. The detection unit detects a data amount of data written to a different memory area among the memory areas when the garbage collection is executed, for each of the memory areas. The management unit manages a threshold set for each of the memory areas. The selection unit selects, based on the data amount and the threshold for each of the memory areas, a memory area whose data amount is smaller than the threshold of the memory area. The garbage collection unit executes the garbage collection on the memory area selected by the selection unit.
    • 根据一个实施例,存储器系统包括非易失性存储器,检测单元,管理单元,选择单元和垃圾收集单元。 非易失性存储器包括分为垃圾回收执行单元的存储区域。 对于每个存储区域,检测单元检测在执行垃圾收集时的存储区域中写入不同存储区域的数据量。 管理单元管理针对每个存储区域设置的阈值。 选择单元基于每个存储区域的数据量和阈值来选择数据量小于存储区域的阈值的存储区域。 垃圾收集单元在由选择单元选择的存储区域上执行垃圾收集。