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111. 发明授权

US07111200B2 Apparatus and method for debugging a logical partition 有权
标题翻译：用于调试逻辑分区的装置和方法
公开(公告)号：US07111200B2
公开(公告)日：2006-09-19
申请号：US10418323
申请日：2003-04-17
申请人： Troy David Armstrong , William Joseph Armstrong , Tracy Bashore , George F. Eckman , Naresh Nayar
发明人： Troy David Armstrong , William Joseph Armstrong , Tracy Bashore , George F. Eckman , Naresh Nayar
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/362
摘要： A logical partition debugger allows debugging one logical partition in a computer system without requiring the shutdown of other logical partitions. The logical partition debugger is implemented in software in the partition manager. The logical partition debugger provides many common debug functions known in existing hardware and software debuggers, but does so in a manner that only the partition being debugged is affected.
摘要翻译：逻辑分区调试器允许在计算机系统中调试一个逻辑分区，而不需要关闭其他逻辑分区。逻辑分区调试器在分区管理器中的软件中实现。逻辑分区调试器提供了现有硬件和软件调试器中已知的许多常见的调试功能，但这样做的方式只有被调试的分区受到影响。

112. 发明授权

US07058782B2 Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism 失效
标题翻译：用于协调动态内存释放与冗余位线转向机制的方法和装置
公开(公告)号：US07058782B2
公开(公告)日：2006-06-06
申请号：US10631067
申请日：2003-07-31
申请人： Daniel James Henderson , Alongkorn Kitamorn , Wayne L. Lemmon , Naresh Nayar , Ravi A. Shankar
发明人： Daniel James Henderson , Alongkorn Kitamorn , Wayne L. Lemmon , Naresh Nayar , Ravi A. Shankar
IPC分类号： G06F12/00
CPC分类号： G11C29/42 , G06F11/106 , G11C29/70 , G11C2029/0409
摘要： A method and apparatus for coordinating dynamic memory page deallocation with a redundant bit line steering mechanism are provided. With the method and apparatus, memory scrubbing and redundant bit line steering operations are performed in parallel with handling of notifications of runtime correctable errors. When a correctable error is encountered during runtime, and the correctable error is determined to be persistent, then dynamic memory page deallocation is requested of a hypervisor. The determination of persistence is based on a history CE table that is populated by the operation of the memory scrubbing and redundant bit line steering mechanism of a service processor. Thus, only those correctable errors that persist for longer than one memory scrubbing cycle are subject to memory page deallocation.
摘要翻译：提供了一种用于与冗余位线转向机构协调动态存储器页面解除分配的方法和装置。利用该方法和装置，与处理运行时可校正错误的通知并行执行存储器擦除和冗余位线转向操作。当在运行时遇到可纠正的错误，并且确定可纠正的错误是持久的，则请求虚拟机管理程序的动态内存页解除分配。持久性的确定基于由服务处理器的存储器擦除和冗余位线转向机制的操作填充的历史CE表。因此，只有那些持续时间超过一个内存擦除周期的可纠正错误才会受到内存页解除分配。

113. 发明授权

US06976100B2 Autonomic I/O adapter response performance optimization using polling 失效
标题翻译：自适应I / O适配器响应性能优化使用轮询
公开(公告)号：US06976100B2
公开(公告)日：2005-12-13
申请号：US10424198
申请日：2003-04-25
申请人： Shelly Marie Dirstine , Naresh Nayar , Gregory Michael Nordstrom
发明人： Shelly Marie Dirstine , Naresh Nayar , Gregory Michael Nordstrom
IPC分类号： G06F3/00
CPC分类号： G06F9/546 , G06F9/4881 , G06F2209/548
摘要： Methods, systems, and articles of manufacture for communicating with an I/O processor (IOP) are provided. Polling of message queue pointers is utilized to detect the occurrence of certain message queue related events, rather than rely on interrupts generated by the IOP. The polling may decrease the disruptive effects of IOP generated interrupts. In an effort to minimize the latency associated with detecting IOP related events, the polling may be initiated frequently by an operating system task dispatcher. In an effort to minimize context switches, the task dispatcher may schedule the processing of upstream messages detected while polling to coincide with naturally occurring task swaps.
摘要翻译：提供了与I / O处理器（IOP）通信的方法，系统和制品。消息队列指针的轮询用于检测某些消息队列相关事件的发生，而不是依赖于IOP生成的中断。轮询可能会减少IOP产生的中断的破坏性影响。为了最小化与检测IOP相关事件相关联的延迟，轮询可以由操作系统任务分派器频繁地启动。为了最小化上下文切换，任务调度器可以调度在轮询期间检测到的上行消息的处理以与自然发生的任务交换重合。

114. 发明授权

US06467007B1 Processor reset generated via memory access interrupt 失效
标题翻译：通过存储器访问中断产生处理器复位
公开(公告)号：US06467007B1
公开(公告)日：2002-10-15
申请号：US09314769
申请日：1999-05-19
申请人： Troy David Armstrong , William Joseph Armstrong , Naresh Nayar , Kenneth Charles Vossen
发明人： Troy David Armstrong , William Joseph Armstrong , Naresh Nayar , Kenneth Charles Vossen
IPC分类号： G06F1324
CPC分类号： G06F11/0712 , G06F1/24 , G06F11/073 , G06F11/0793
摘要： An apparatus, program product, and method utilize a memory access interrupt to effect a reset of a processor in a multi-processor environment. Specifically, a source processor is permitted to initiate a reset of a target processor simply by generating both a reset request and a memory access interrupt for the target processor. The target processor is then specifically configured to detect the presence of a pending reset request during handing of the memory access interrupt, such that the target processor will perform a reset operation responsive to detection of such a request.
摘要翻译：一种装置，程序产品和方法利用存储器访问中断来实现多处理器环境中的处理器的复位。具体来说，源处理器被简单地通过产生目标处理器的复位请求和存储器访问中断来允许目标处理器的复位。然后，目标处理器被特别地配置成在处理存储器访问中断期间检测到待处理复位请求的存在，使得目标处理器将响应于对这种请求的检测而执行复位操作。

115. 发明申请

US20130179892A1 PROVIDING LOGICAL PARTIONS WITH HARDWARE-THREAD SPECIFIC INFORMATION REFLECTIVE OF EXCLUSIVE USE OF A PROCESSOR CORE 有权
公开(公告)号：US20130179892A1
公开(公告)日：2013-07-11
申请号：US13345002
申请日：2012-01-06
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/46 , G06F13/24
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

116. 发明授权

US08407515B2 Partition transparent memory error handling in a logically partitioned computer system with mirrored memory 有权
标题翻译：在具有镜像内存的逻辑分区计算机系统中分区透明内存错误处理
公开(公告)号：US08407515B2
公开(公告)日：2013-03-26
申请号：US12115625
申请日：2008-05-06
申请人： Peter Joseph Heyrman , Naresh Nayar , Gary Ross Ricard
发明人： Peter Joseph Heyrman , Naresh Nayar , Gary Ross Ricard
IPC分类号： G06F11/00
CPC分类号： G06F11/2082 , G06F11/2094
摘要： A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error.
摘要翻译：用于透明地处理镜像存储器系统中的可重复校正错误和不可校正错误的方法和装置防止由于不可校正的存储器错误而导致的可校正存储器错误或系统故障的昂贵的系统关闭。当对于给定的存储器位置检测到大量的可校正错误时，管理程序中的存储器重定位机制将与存储器位置相关联的数据透明地移动到备用物理存储器位置到分区，使得分区不知道物理内存实现内存位置已更改。当发生可纠正错误时，内存重定位机制使用来自伙伴镜像内存块的数据作为具有不可校正错误的存储器块的数据源，然后将数据重新定位到新分配的存储器块以用不可校正的错误来替换存储器块。

117. 发明授权

US08381002B2 Transparently increasing power savings in a power management environment 失效
公开(公告)号：US08381002B2
公开(公告)日：2013-02-19
申请号：US12821789
申请日：2010-06-23
申请人： Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III
发明人： Naresh Nayar , Karthick Rajamani , Freeman L. Rawson, III
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
摘要： A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode.

118. 发明授权

US08341628B2 Controlling depth and latency of exit of a virtual processor's idle state in a power management environment 失效
标题翻译：在电源管理环境中控制虚拟处理器空闲状态退出的深度和延迟
公开(公告)号：US08341628B2
公开(公告)日：2012-12-25
申请号：US12645597
申请日：2009-12-23
申请人： Richard Louis Arndt , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal Craig Swanberg
发明人： Richard Louis Arndt , Christopher Francois , Naresh Nayar , Karthick Rajamani , Freeman Leigh Rawson, III , Randal Craig Swanberg
IPC分类号： G06F9/455 , G06F1/00
CPC分类号： G06F9/45533 , G06F9/45541 , G06F2009/45575
摘要： A mechanism is provided in a logically partitioned data processing system for controlling depth and latency of exit of a virtual processor's idle state. A virtualization layer generates a cede latency setting information (CLSI) data. Responsive to booting a logical partition, the virtualization layer communicates the CLSI data to an operating system (OS) of the logical partition. The OS determines, based on the CLSI data, a particular idle state of a virtual processor under a control of the OS. Responsive to the OS calling the virtualization layer, the OS communicates the particular idle state of the virtual processor to the virtualization layer for assigning the particular idle state and wake-up characteristics to the virtual processor.
摘要翻译：在逻辑分区的数据处理系统中提供一种机制，用于控制虚拟处理器的空闲状态的退出的深度和等待时间。一个虚拟化层产生一个雪松延迟设置信息（CLSI）数据。响应于引导逻辑分区，虚拟化层将CLSI数据传送到逻辑分区的操作系统（OS）。 OS根据CLSI数据确定在OS控制下的虚拟处理器的特定空闲状态。响应于调用虚拟化层的OS，OS将虚拟处理器的特定空闲状态传送到虚拟化层，以将特定的空闲状态和唤醒特性分配给虚拟处理器。

119. 发明授权

US08255639B2 Partition transparent correctable error handling in a logically partitioned computer system 失效
标题翻译：逻辑分区计算机系统中的分区透明可校正错误处理
公开(公告)号：US08255639B2
公开(公告)日：2012-08-28
申请号：US12115613
申请日：2008-05-06
申请人： Peter Joseph Heyrman , Naresh Nayar , Gary Ross Ricard
发明人： Peter Joseph Heyrman , Naresh Nayar , Gary Ross Ricard
IPC分类号： G06F12/16 , G06F12/06
CPC分类号： G06F13/28
摘要： A method and apparatus for transparently handling recurring correctable errors to prevent costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. Similarly, the hypervisor can move direct memory access (DMA) memory locations using an I/O translation table.
摘要翻译：一种用于透明地处理重复的可纠正错误以防止由于不可校正的存储器错误而导致的可校正的存储器错误或系统故障的昂贵的系统关闭的方法和装置。当对于给定的存储器位置检测到大量可校正错误时，管理程序将与存储器位置相关联的数据透明地移动到备用物理存储器位置到分区，使得分区不知道物理存储器实现存储器位置已经变了。类似地，管理程序可以使用I / O转换表移动直接存储器访问（DMA）存储器位置。

120. 发明授权

US08234645B2 Deallocation of computer data in a multithreaded computer 失效
公开(公告)号：US08234645B2
公开(公告)日：2012-07-31
申请号：US11970816
申请日：2008-01-08
申请人： William Joseph Armstrong , Peter Joseph Heyrman , Naresh Nayar
发明人： William Joseph Armstrong , Peter Joseph Heyrman , Naresh Nayar
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/5016 , G06F9/5022 , Y10S707/99953 , Y10S707/99957
摘要： An apparatus, program product and method support the deallocation of a data structure in a multithreaded computer without requiring the use of computationally expensive semaphores or spin locks. Specifically, access to a data structure is governed by a shared pointer that, when a request is received to deallocate the data structure, is initially set to a value that indicates to any thread that later accesses the pointer that the data structure is not available. In addition, to address any thread that already holds a copy of the shared pointer, and thus is capable of accessing the data structure via the shared pointer after the initiation of the request, all such threads are monitored to determine whether any thread is still using the shared pointer by determining whether any thread is executing program code that is capable of using the shared pointer to access the data structure. Once this condition is met, it is ensured that no thread can potentially access the data structure via the shared pointer, and as such, the data structure may then be deallocated.

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