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111. 发明授权

US06876089B2 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer 失效
标题翻译：使用各向异性导电层测试和组装凸起装置的装置和方法
公开(公告)号：US06876089B2
公开(公告)日：2005-04-05
申请号：US10338541
申请日：2003-01-07
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R1/04 , H01L21/60 , H01L23/13 , H01L23/48 , H01L23/498 , H05K3/32 , H01L23/52 , H01L29/40
CPC分类号： H01L23/13 , G01R1/0466 , G01R1/0483 , H01L23/49827 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16237 , H01L2224/8114 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/15174 , H05K3/325 , H05K3/326 , H01L2224/05599
摘要： The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads. In another embodiment, an apparatus for testing a bumped device having a plurality of conductive bumps includes a substrate having a plurality of contact pads distributed thereon and substantially alignable with the plurality of conductive bumps, and an anisotropically conductive layer disposed on the first surface and engageable with the plurality of conductive bumps to electrically couple each of the conductive bumps with a corresponding one of the contact pads. Alternately, the test apparatus may also include an alignment device or a bumped device handler. In another embodiment, a method of testing a bumped device includes engaging a plurality of contact pads with an anisotropically conductive layer, engaging the plurality of conductive bumps with the anisotropically conductive layer substantially opposite from and in approximate alignment with the plurality of contact pads, forming a plurality of conductive paths through the anisotropically conductive layer so that each of the conductive bumps is electrically coupled to one of the contact pads, and applying test signals through at least some of the contact pads and the conductive paths to at least some of the conductive bumps.
摘要翻译：本发明涉及使用各向异性导电层测试和组装凸模和凸起装置的装置和方法。在一个实施例中，半导体器件包括具有形成在其上的多个导电凸起的凸起器件，衬底，其上分布有多个接触焊盘并且与多个导电凸块大致对准，并且各向异性导电层设置在机械耦合到凸起的装置和衬底。各向异性导电层将每个导电凸块与对应的一个接触垫电耦合。在另一个实施例中，一种用于测试具有多个导电凸块的凸起器件的设备包括：衬底，其具有分布在其上的多个接触焊盘并且可与多个导电凸块基本对准，以及设置在第一表面上并可接合的各向异性导电层其中多个导电凸块将每个导电凸块与相应的一个接触垫电耦合。或者，测试装置还可以包括对准装置或凸起的装置处理器。在另一个实施例中，一种测试凸起装置的方法包括：将多个接触垫与各向异性导电层接合，使多个导电凸块与多个接触垫基本上相对并与其大致对准的各向异性导电层接合，形成通过各向异性导电层的多个导电路径，使得每个导电凸块电耦合到一个接触焊盘，以及将测试信号通过至少一些接触焊盘和导电路径施加到至少一些导电颠簸

112. 发明授权

US06529027B1 Interposer and methods for fabricating same 失效
标题翻译：插件及其制造方法
公开(公告)号：US06529027B1
公开(公告)日：2003-03-04
申请号：US09533407
申请日：2000-03-23
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R3102
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，其包括接纳半导体器件（例如倒装芯片型半导体器件）与栅介质基板的栅栏。栅栏可以包括被配置为使半导体器件与插入器衬底逐渐对准的边缘。挡板还可以包括一个或多个侧向凹入区域，以便于半导体器件与插入器基板的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向应用于一层或多层以形成栅栏。结果，内插器基板不需要精确地机械对准。

113. 发明授权

US06414506B1 Interconnect for testing semiconductor dice having raised bond pads 有权
公开(公告)号：US06414506B1
公开(公告)日：2002-07-02
申请号：US09213573
申请日：1998-12-17
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： G01R3126
摘要： A method for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) and a method for forming an interconnect suitable for testing this type of dice are provided. The interconnect includes a substrate having contact members comprising an array of sharpened elongated projections. The sharpened projections are formed by etching (or by growing and removing an oxide) through exposed areas of a mask. A conductive layer is formed on the sharpened projections and is in electrical communication with conductive traces formed on the substrate. The conductive layer can be formed as a layer of metal, as a stack of metals including a barrier metal, as a silicide, or as a layer of polysilicon. For testing an unpackaged die, the interconnect and die are placed in a temporary carrier and biased together. The sharpened projections are adapted to penetrate the contact location on the die to a limited penetration depth to establish an ohmic connection while minimizing damage to the contact location.

114. 发明授权

US6150717A Direct die contact (DDC) semiconductor package 失效
标题翻译：直接裸片接触（DDC）半导体封装
公开(公告)号：US6150717A
公开(公告)日：2000-11-21
申请号：US98197
申请日：1998-06-16
申请人： Alan G. Wood , Warren M. Farnworth , Ford Grigg , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , Ford Grigg , Salman Akram
IPC分类号： H01L21/60 , H01L23/485 , H01L23/48
CPC分类号： H01L24/81 , H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05571 , H01L2224/10165 , H01L2224/13099 , H01L2224/131 , H01L2224/1319 , H01L2224/16237 , H01L2224/81136 , H01L2224/8114 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81365 , H01L2224/81801 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517
摘要： A semiconductor package and method for fabricating the package are provided. The package includes a housing having individual channels, each adapted to retain a semiconductor die in electrical communication with electrical connectors. The dice can include solder bumps, formed on electrodes, using electroless deposition and wave soldering. For fabricating the package, the dice can be inserted into the channels, with the electrical connectors on the housing proximate to the solder bumps on the dice. The solder bumps can then be reflowed to form bonded connections with the electrical connectors. In an alternate embodiment, conductive adhesive bumps, rather than solder bumps, are formed on the dice to provide compliant connections with the electrical connectors on the housing. In addition, the conductive adhesive bumps can be cured while in contact with the electrical connectors to form bonded connections. Other alternate embodiments include a chip scale package, a temporary package for testing bare dice, and a multi chip module.
摘要翻译：提供一种用于制造封装的半导体封装和方法。封装包括具有单独通道的壳体，每个通道适于保持与电连接器电连通的半导体管芯。骰子可以包括使用无电沉积和波峰焊在电极上形成的焊料凸块。为了制造封装，可以将骰子插入通道中，外壳上的电连接器靠近骰子上的焊料凸块。然后可以将焊料凸起回流以与电连接器形成粘合连接。在替代实施例中，导电粘合剂凸块而不是焊料凸块形成在芯片上，以提供与壳体上的电连接器的柔性连接。此外，导电粘合剂凸块可以在与电连接器接触的同时固化，以形成接合连接。其他替代实施例包括芯片级封装，用于测试裸裸片的临时封装以及多芯片模块。

115. 发明授权

US6114240A Method for fabricating semiconductor components using focused laser beam 有权
标题翻译：使用聚焦激光束制造半导体元件的方法
公开(公告)号：US6114240A
公开(公告)日：2000-09-05
申请号：US250289
申请日：1999-02-12
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L21/48 , H01L21/60 , H01L21/768 , H01L23/13 , H01L23/498 , H01L23/538 , H01L25/10 , H05K1/03 , H05K1/11 , H05K3/00 , H01L21/44
CPC分类号： H05K1/112 , H01L21/486 , H01L21/76898 , H01L23/13 , H01L23/49827 , H01L23/5389 , H01L25/105 , H01L2224/05001 , H01L2224/05023 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/16237 , H01L2224/82039 , H01L2225/1005 , H01L2924/01004 , H01L2924/01006 , H01L2924/01009 , H01L2924/01013 , H01L2924/0102 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H05K1/0306 , H05K2201/09472 , H05K2201/0959 , H05K2201/09827 , H05K2201/09845 , H05K2201/10674 , H05K2201/10734 , H05K3/0029 , H05K3/0032
摘要： A method for fabricating semiconductor components, such as packages, interconnects and test carriers, is provided. The method includes laser machining conductive vias for interconnecting contacts on the component, using a laser beam that is focused to produce a desired via geometry. The vias can include enlarged end portions to facilitate deposition of a conductive material during formation of the vias, and to provide an increased surface area for forming the contacts. For example, by focusing the laser beam at a midpoint of a substrate of the component, an hour glass via geometry is provided. Alternately, the laser beam can be focused at an exit point, or at an entry point of the substrate, to provide converging or diverging via geometries. The method can also include forming contact pins on the conductive vias by bonding and shaping metal wires using a wire bonding process, or a welding process.
摘要翻译：提供了一种制造诸如封装，互连和测试载体的半导体部件的方法。该方法包括激光加工用于使部件上的触点互连的导电通孔，使用聚焦以产生所需通孔几何形状的激光束。通孔可以包括扩大的端部，以便于在形成通孔期间沉积导电材料，并且提供用于形成触点的增加的表面积。例如，通过将激光束聚焦在部件的基板的中点处，提供了小时玻璃通孔几何形状。或者，激光束可以在出口点处或在基板的入口处聚焦，以提供会聚或发散的几何形状。该方法还可以包括通过使用引线接合工艺或焊接工艺接合和成形金属线来在导电通孔上形成接触引脚。

116. 发明授权

US6020624A Semiconductor package with bi-substrate die 失效
标题翻译：半导体封装采用双衬底裸片
公开(公告)号：US6020624A
公开(公告)日：2000-02-01
申请号：US53273
申请日：1998-04-01
申请人： Alan G. Wood , Salman Akram , Warren M. Farnworth
发明人： Alan G. Wood , Salman Akram , Warren M. Farnworth
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , H01L29/06 , H01L23/02 , H01L23/28
CPC分类号： H05K3/4007 , G01R1/0466 , G01R1/0483 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , H01L24/85 , G01R1/06738 , G01R1/0735 , G01R3/00 , G01R31/2831 , G01R31/2863 , H01L2224/16145 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/4847 , H01L2224/73207 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01072 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A method for forming an interconnect for semiconductor devices is provided. The interconnect includes raised contact structures covered with a conductive layer and having penetrating projections for penetrating contacts for the semiconductor devices. In an illustrative embodiment, the interconnect can be used to form a bi-substrate die. An interconnect substrate for the bi-substrate die includes control and logic circuitry and a memory substrate for the bi-substrate die includes a memory array. The interconnect can also be used to establish an electrical connection to microscopic contacts formed on a conventional die. In addition, the interconnect can be formed with three dimensional micro structures for contacting the microscopic contacts. Still further, the interconnect can be formed as wafer interconnect for electrically contacting dice contained on a wafer or for stacking multiple wafers.
摘要翻译：提供一种用于形成用于半导体器件的互连的方法。互连包括被导电层覆盖的凸起的接触结构，并且具有用于穿透用于半导体器件的触点的穿透突起。在说明性实施例中，互连可用于形成双衬底裸片。用于双衬底裸片的互连衬底包括控制和逻辑电路，并且用于双衬底裸片的存储器衬底包括存储器阵列。互连还可用于建立与常规裸片上形成的微观触点的电连接。此外，互连可以由用于接触微观触点的三维微结构形成。此外，互连可以形成为用于电接触包含在晶片上的骰子或用于堆叠多个晶片的晶片互连。

117. 发明授权

US5904546A Method and apparatus for dicing semiconductor wafers 失效
标题翻译：用于切割半导体晶片的方法和装置
公开(公告)号：US5904546A
公开(公告)日：1999-05-18
申请号：US605245
申请日：1996-02-12
申请人： Alan G. Wood , Warren M. Farnworth , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , Salman Akram
IPC分类号： H01L21/301 , H01L21/78 , H01L21/46
CPC分类号： H01L21/78
摘要： A method and apparatus for dicing semiconductor wafers is provided. The method comprises: forming an etch mask on the wafer, and then etching the wafer with a wet etchant, such as KOH, to form a peripheral groove around each die. Etching the wafer can be from the front side of the wafer, from the back side of the wafer or with partial etches from both sides. The etch process can be performed on a single wafer using a spray head apparatus or on batches of wafers using a recirculating dip tank apparatus.
摘要翻译：提供了一种用于切割半导体晶片的方法和装置。该方法包括：在晶片上形成蚀刻掩模，然后用诸如KOH的湿蚀刻剂蚀刻晶片，以在每个管芯周围形成周边凹槽。蚀刻晶片可以从晶片的前侧，从晶片的背面或两侧部分蚀刻。可以使用喷头装置或使用循环浸渍槽装置的一批晶片在单个晶片上进行蚀刻工艺。

118. 发明授权

US5592736A Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads 失效
标题翻译：制造用于测试未包装的半导体晶片的互连件，其具有凸起的焊盘
公开(公告)号：US5592736A
公开(公告)日：1997-01-14
申请号：US369067
申请日：1995-01-05
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H05K1/03 , H05K3/32 , H05K3/40 , H05K3/00
CPC分类号： H05K3/4007 , H01L2224/0401 , H01L2224/05557 , H01L2224/81191 , H01L2924/10253 , H05K1/0306 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , H05K3/325 , Y10T29/49146
摘要： A method for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) and a method for forming an interconnect suitable for testing this type of dice are provided. The interconnect includes a substrate having contact members comprising an array of sharpened elongated projections. The sharpened projections are formed by etching (or by growing and removing an oxide) through exposed areas of a mask. A conductive layer is formed on the sharpened projections and is in electrical communication with conductive traces formed on the substrate. The conductive layer can be formed as a layer of metal, as a stack of metals including a barrier metal, as a silicide, or as a layer of polysilicon. For testing an unpackaged die, the interconnect and die are placed in a temporary carrier and biased together. The sharpened projections are adapted to penetrate the contact location on the die to a limited penetration depth to establish an ohmic connection while minimizing damage to the contact location.
摘要翻译：提供了一种用于测试具有凸起的接触位置（例如，凸起的接合焊盘）的未封装半导体裸片的方法和用于形成适于测试这种类型的骰子的互连的方法。互连包括具有包括锐化的细长突起阵列的接触构件的衬底。通过掩模的暴露区域的蚀刻（或通过生长和去除氧化物）形成锐化的突起。导电层形成在锐化的突起上并与形成在衬底上的导电迹线电连通。导电层可以形成为金属层，作为包括阻挡金属的金属叠层，作为硅化物，或者形成为多晶硅层。为了测试未封装的裸片，将互连和裸片放置在临时载体中并偏置在一起。尖锐的突起适于穿透模具上的接触位置到有限的穿透深度，以建立欧姆连接，同时最小化对接触位置的损害。

119. 发明授权

US5483741A Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice 失效
标题翻译：制造用于测试裸半导体晶片的自限硅基互连的方法
公开(公告)号：US5483741A
公开(公告)日：1996-01-16
申请号：US335267
申请日：1994-11-07
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： G01R1/06 , B81C1/00 , G01R1/067 , G01R1/073 , H01L21/66 , H05K1/03 , H05K3/32 , H05K3/02
CPC分类号： G01R1/06738 , G01R1/07314 , H01L2224/13019 , H05K1/0306 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , H05K3/325 , Y10T29/49155 , Y10T29/49453
摘要： A method for forming a self-limiting, silicon based interconnect for making temporary electrical contact with bond pads on a semiconductor die is provided. The interconnect includes a silicon substrate having an array of contact members adapted to contact the bond pads on the die for test purposes (e.g., burn-in testing). The interconnect is fabricated by: forming the contact members on the substrate; forming a conductive layer on the tip of the contact members; and then forming conductive traces to the conductive layer. The conductive layer is formed by depositing a silicon containing layer (e.g., polysilicon, amorphous silicon) and a metal layer (e.g., titanium, tungsten, platinum) on the substrate and contact members. These layers are reacted to form a silicide. The unreacted metal and silicon containing layer are then etched selective to the conductive layer which remains on the tip of the contact members. Conductive traces are then formed in contact with the conductive layer using a suitable metallization process. Bond wires are attached to the conductive traces and may be attached to external test circuitry. Alternately, another conductive path such as external contacts (e.g., slide contacts) may provide a conductive path between the conductive traces and external circuitry. The conductive layer, conductive traces and bond wires provide a low resistivity conductive path from the tips of the contact members to external test circuitry.
摘要翻译：提供一种用于形成用于与半导体管芯上的接合焊盘暂时电接触的自限制硅基互连的方法。互连包括具有适于接触芯片上的接合焊盘的接触部件阵列的硅基板用于测试目的（例如，老化测试）。互连通过以下方式制造：在基板上形成接触构件; 在所述接触构件的尖端上形成导电层; 然后在导电层上形成导电迹线。导电层通过在衬底和接触构件上沉积含硅层（例如，多晶硅，非晶硅）和金属层（例如，钛，钨，铂）形成。使这些层反应形成硅化物。然后将未反应的含金属和硅的层选择性地蚀刻到保留在接触构件的尖端上的导电层。然后使用合适的金属化工艺将导电迹线形成为与导电层接触。接合线连接到导电迹线，并且可以附接到外部测试电路。或者，诸如外部触点（例如，滑动触点）的另一导电路径可以在导电迹线和外部电路之间提供导电路径。导电层，导电迹线和接合线提供从接触构件的尖端到外部测试电路的低电阻率导电路径。

120. 发明授权

US08786097B2 Method of forming vias in semiconductor substrates and resulting structures 有权
标题翻译：在半导体衬底和结构中形成通孔的方法
公开(公告)号：US08786097B2
公开(公告)日：2014-07-22
申请号：US12955359
申请日：2010-11-29
申请人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
发明人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898
摘要： Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.
摘要翻译：公开了在半导体衬底中形成贯通孔的方法和所得到的结构。在一个实施例中，可以通过从活性表面通过其上的导电元件和导电元件下面的基底的一部分形成部分通孔来形成通孔。然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。在另一个实施例中，部分通孔可以通过激光烧蚀或从衬底的背面钻孔到其中的预定距离来形成。通孔可以通过形成延伸通过导电元件和下面的衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。在另一个实施例中，可以首先通过激光烧蚀或从衬底的背面进行钻孔形成部分通孔，然后通过干蚀刻来完成通孔。

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