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111. 发明授权

US06798017B2 Vertical dual gate field effect transistor 有权
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US06798017B2
公开(公告)日：2004-09-28
申请号：US09944665
申请日：2001-08-31
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
IPC分类号： H01L2976
CPC分类号： H01L29/78642 , H01L21/2255 , H01L21/76897 , H01L21/823487 , H01L27/088 , H01L29/66666 , H01L29/7827 , H01L29/7831
摘要： A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
摘要翻译：特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻或外延生长形成的半导体柱的相对侧上的潜在的独立栅极结构。栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。柱的上端由盖和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

112. 发明授权

US06596597B2 Method of manufacturing dual gate logic devices 失效
标题翻译：制造双门逻辑器件的方法
公开(公告)号：US06596597B2
公开(公告)日：2003-07-22
申请号：US09879590
申请日：2001-06-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
IPC分类号： H01L21336
CPC分类号： H01L29/66484 , H01L21/2807 , H01L29/7831 , H01L29/78645 , H01L29/78648
摘要： The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.
摘要翻译：本发明的特征在于双栅极或双栅极逻辑器件，其包含一致的自对准并且具有恒定宽度的沟道的栅极导体。本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。以这种方式，可以将栅极导体封装在电介质壳体中而不改变硅沟道的长度。采用单晶硅晶片作为通道材料。自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。

113. 发明授权

US06506660B2 Semiconductor with nanoscale features 失效
标题翻译：半导体具有纳米级特征
公开(公告)号：US06506660B2
公开(公告)日：2003-01-14
申请号：US10008092
申请日：2001-11-13
申请人： Steven J. Holmes , Charles Black , David J. Frank , Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William Hsioh-Lien Ma , Keith R. Milkove , Kathryn W. Guarini
发明人： Steven J. Holmes , Charles Black , David J. Frank , Toshiharu Furukawa , Mark C. Hakey , David V. Horak , William Hsioh-Lien Ma , Keith R. Milkove , Kathryn W. Guarini
IPC分类号： H01L2120
CPC分类号： H01L28/92
摘要： Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.
摘要翻译：描述了通过在半导体介质上提供第一固态电极图案来增加半导体电容器的电容的方法，以有效增加所述第一电极图案的表面积的方式蚀刻所述第一电极图案上的地形特征，所述电极图案上的电介质层基本上符合所述形貌特征，并且在所述电介质层上沉积第二固态电极图案，并且与所述第一固态电极图案充分绝缘，从而产生具有所述第一固态的电容电极图案。

114. 发明授权

US06429045B1 Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage 失效
标题翻译：多芯片贴片的结构和工艺，减少了静电放电的危害
公开(公告)号：US06429045B1
公开(公告)日：2002-08-06
申请号：US09779215
申请日：2001-02-07
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , H. Bernhard Pogge , Edmund J. Sprogis , Steven H. Voldman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , H. Bernhard Pogge , Edmund J. Sprogis , Steven H. Voldman
IPC分类号： H01L2144
CPC分类号： H01L29/0657 , H01L21/563 , H01L23/544 , H01L24/81 , H01L25/0655 , H01L2223/54473 , H01L2224/16 , H01L2224/73203 , H01L2224/81005 , H01L2224/81007 , H01L2224/81136 , H01L2924/01078 , H01L2924/01079 , H01L2924/10158 , Y10S438/928 , H01L2924/00012
摘要： A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.
摘要翻译：一种制造精密对准宏（PAM）的技术，降低了静电放电损伤和热损伤的风险。通过单个芯片的背面提供电接触和热接触到支撑硅衬底。用于电镀的导电种子层形成在支撑衬底上。在种子层上形成电介质（优选为热）层。通孔形成在热层中，金属触点形成在通孔中。将两个以上的芯片的正面接合在取向基板的顶面上，将芯片与取向基板对准。芯片的背面通过热和压力结合到金属触点和热层。取出对准基板。芯片的正面平面化。最后，在芯片和热层上形成互连布线。

115. 发明授权

US06376873B1 Vertical DRAM cell with robust gate-to-storage node isolation 失效
标题翻译：垂直DRAM单元具有鲁棒的栅极到存储节点隔离
公开(公告)号：US06376873B1
公开(公告)日：2002-04-23
申请号：US09287410
申请日：1999-04-07
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jeffrey J. Welser
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky , Jeffrey J. Welser
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876
摘要： A dynamic random access memory device formed in a substrate having a trench. The trench has a side wall, a top, a lower portion, and a circumference. The device includes a signal storage node including a storage node conductor formed in the lower portion of the trench and isolated from the side wall by a node dielectric and a collar oxide above the node dielectric. A buried strap is coupled to the storage node conductor and contacts a portion of the side wall of the trench above the collar oxide. A trench-top dielectric which is formed upon the buried strap has a trench-top dielectric thickness. A signal transfer device includes a first diffusion region extending into the substrate adjacent the portion of the trench side wall contacted by the buried strap, a gate insulator having a gate insulator thickness formed on the trench side wall above the first buried strap, wherein the gate insulator thickness is less than the trench-top dielectric thickness, and a gate conductor formed within the trench upon the trench-top dielectric and adjacent the gate insulator.
摘要翻译：形成在具有沟槽的衬底中的动态随机存取存储器件。沟槽具有侧壁，顶部，下部和圆周。该装置包括信号存储节点，该信号存储节点包括形成在沟槽下部的存储节点导体，并且通过节点电介质和节点电介质上方的环形氧化物与侧壁隔离。埋置的带子耦合到存储节点导体并且与套环氧化物上方的沟槽的侧壁的一部分接触。形成在掩埋带上的沟槽电介质具有沟槽顶部的介电厚度。信号传送装置包括：第一扩散区域，其延伸到与所述掩埋带接触的所述沟槽侧壁的所述部分相邻的所述衬底;门绝缘体，其具有形成在所述第一掩埋带的上方的所述沟槽侧壁上的栅绝缘体厚度，绝缘体厚度小于沟槽顶部电介质厚度，以及形成在沟槽顶部电介质并且邻近栅极绝缘体的沟槽内的栅极导体。

116. 发明授权

US06323082B1 Process for making a DRAM cell with three-sided gate transfer 失效
标题翻译：用于制造具有三面栅极转移的DRAM单元的工艺
公开(公告)号：US06323082B1
公开(公告)日：2001-11-27
申请号：US09565504
申请日：2000-05-05
申请人： Toshiharu Furukawa , David V. Horak , Steven J. Holmes , Mark C. Hakey , Jack A. Mandelman
发明人： Toshiharu Furukawa , David V. Horak , Steven J. Holmes , Mark C. Hakey , Jack A. Mandelman
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L29/7851 , Y10S257/906 , Y10S438/947
摘要： A DRAM device and a process of manufacturing the device. The DRAM device includes a bit-line coupled to a signal storage node through a transfer device that is controlled by a word line. The transfer device includes a mesa structure having a first end, a second end opposite the first end, a top, a first side, and a second side opposite the first side. A bit-line diffusion region couples the first end of the mesa structure to a bit-line contact. A storage node diffusion region couples the second end of the mesa structure to the signal storage node. The word line controls a channel formed in the mesa structure through a gate which is formed upon the first side, the second side, and the top of the mesa structure. A sub-minimum width of the mesa structure allows full depletion to be easily achieved, resulting in volume inversion in the channel.
摘要翻译： DRAM装置和制造装置的过程。 DRAM装置包括通过由字线控制的传送装置耦合到信号存储节点的位线。转印装置包括具有第一端，与第一端相对的第二端，顶部，第一侧和与第一侧相对的第二侧的台面结构。位线扩散区域将台面结构的第一端耦合到位线接触。存储节点扩散区将台面结构的第二端耦合到信号存储节点。字线通过形成在台面结构的第一面，第二面和顶部上的栅极来控制形成在台面结构中的通道。台面结构的亚最小宽度允许容易地实现完全耗尽，导致通道中的体积反转。

117. 发明授权

US06319759B1 Method for making oxide 失效
标题翻译：氧化物的制造方法
公开(公告)号：US06319759B1
公开(公告)日：2001-11-20
申请号：US09131828
申请日：1998-08-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
IPC分类号： H01L2100
CPC分类号： H01L21/28185 , H01L21/268 , H01L21/28211 , H01L21/31662 , H01L21/823462 , H01L21/823481
摘要： A method of forming oxide and gate oxide areas of differing thicknesses. The processes disclosed include using an electromagnetic wave light at differing exposure durations and/or different energy levels to create oxide of differing thicknesses on a layer. The electromagnetic wave is preferably a laser.
摘要翻译：一种形成不同厚度的氧化物和栅极氧化物区域的方法。所公开的方法包括使用不同曝光持续时间和/或不同能级的电磁波光，以在层上产生不同厚度的氧化物。电磁波优选为激光。

118. 发明授权

US06245488B1 Method for forming features using frequency doubling hybrid resist and device formed thereby 失效
公开(公告)号：US06245488B1
公开(公告)日：2001-06-12
申请号：US09369004
申请日：1999-08-05
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： G03C500
CPC分类号： G03F7/70466 , G03F7/038 , G03F7/2022 , H01L21/0274
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art by providing a method to form unlinked features using hybrid resist. The method uses a trim process in order to trim the linking features from the “loops” formed by the hybrid resist. This allows the method to form a plurality of unlinked features rather than the loops. In order to trim the ends, a relatively larger trim area is formed adjacent the narrow feature line, either by a second exposure step or by utilizing a grey scale reticle. The broader or wider open area allows features to be formed in the narrow feature lines and being trimmed from the relatively large areas, thereby resulting in district features rather than loops.

119. 发明授权

US06210866B1 Method for forming features using self-trimming by selective etch and device formed thereby 失效
标题翻译：使用通过选择性蚀刻的自修整形成特征的方法和由此形成的装置
公开(公告)号：US06210866B1
公开(公告)日：2001-04-03
申请号：US09072031
申请日：1998-05-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： G03F700
CPC分类号： H01L21/3081 , G03F7/16 , H01L21/3086 , H01L21/3088 , H01L27/10873
摘要： The preferred embodiment provides a method for forming unlinked features when using image enhancement techniques. The preferred method is particularly applicable for use in hybrid resist lithographic processes. The method uses a trimming feature embedded in a substrate. The trimming feature acts as a block during a selective etch. This results in unlinked trenches being formed in the substrate. Thus, the preferred method creates unlinked, separate trenches from the “loops” formed by the hybrid resist or other image enhancement techniques. This allows the preferred method to form a plurality of unlinked features rather than the loops or linked features without requiring additional processing steps.
摘要翻译：优选实施例提供了一种用于在使用图像增强技术时形成未链接特征的方法。优选的方法特别适用于混合抗蚀剂光刻工艺中。该方法使用嵌入基板中的修整特征。修整特征在选择性蚀刻期间用作块。这导致在衬底中形成未连接的沟槽。因此，优选的方法与由混合抗蚀剂或其它图像增强技术形成的“环”形成未链接的单独的沟槽。这允许优选的方法形成多个未链接的特征而不是循环或链接的特征，而不需要额外的处理步骤。

120. 发明授权

US06207514B1 Method for forming borderless gate structures and apparatus formed thereby 失效
标题翻译：用于形成无边界门结构的方法及由此形成的装置
公开(公告)号：US06207514B1
公开(公告)日：2001-03-27
申请号：US09224760
申请日：1999-01-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Paul A. Rabidoux
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.
摘要翻译：一种用于在晶体管中形成栅极导体帽的方法，包括以下步骤：a）形成多晶硅栅极导体; b）掺杂多晶硅栅极; c）掺杂扩散区域; 以及d）通过从选择性氮化物沉积和选择性表面氮化中选择的氮化方法来封盖栅极导体。所得到的晶体管可以包括封盖栅极导体和无边界扩散接触，其中通过选择性氮化物沉积和选择性表面氮化中选择的氮化方法发生封盖，并且其中在氮化方法期间掩模一部分栅极导体以留下开口接触区域用于局部互连或门接触。

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