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111. 发明授权

US08536621B2 Quantum-well-based semiconductor devices 有权
标题翻译：量子阱半导体器件
公开(公告)号：US08536621B2
公开(公告)日：2013-09-17
申请号：US13571121
申请日：2012-08-09
申请人： Gilbert Dewey , Marko Radosavljevic , Ravi Pillarisetty , Robert S. Chau , Matthew V. Metz
发明人： Gilbert Dewey , Marko Radosavljevic , Ravi Pillarisetty , Robert S. Chau , Matthew V. Metz
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L29/2003 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
摘要翻译：描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

112. 发明申请

US20130234113A1 QUANTUM WELL MOSFET CHANNELS HAVING LATTICE MISMATCH WITH METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS 审中-公开
标题翻译：具有金属源/漏极的尺寸误差的QUANTUM WELL MOSFET通道，以及合适的反应源/漏极
公开(公告)号：US20130234113A1
公开(公告)日：2013-09-12
申请号：US13870184
申请日：2013-04-25
申请人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L29/15
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译：所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变顶部阻挡层和量子阱的底部缓冲层。

113. 发明申请

US20130143385A1 STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS 失效
公开(公告)号：US20130143385A1
公开(公告)日：2013-06-06
申请号：US13750393
申请日：2013-01-25
申请人： Titash Rakshit , Martin Giles , Ravi Pillarisetty , Jack T. Kavalieros
发明人： Titash Rakshit , Martin Giles , Ravi Pillarisetty , Jack T. Kavalieros
IPC分类号： H01L21/8234
CPC分类号： H01L29/7845 , H01L21/8234 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/0653 , H01L29/495 , H01L29/66795 , H01L29/7831 , H01L29/785
摘要： Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

114. 发明授权

US08350291B2 Modulation-doped multi-gate devices 有权
标题翻译：调制掺杂多栅极器件
公开(公告)号：US08350291B2
公开(公告)日：2013-01-08
申请号：US13248197
申请日：2011-09-29
申请人： Mantu K. Hudait , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Jack T. Kavalieros
发明人： Mantu K. Hudait , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Jack T. Kavalieros
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795
摘要： Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.
摘要翻译：通常描述调制掺杂多栅极器件。在一个示例中，设备包括具有表面的半导体衬底，耦合到半导体衬底的表面的一个或多个缓冲膜，耦合到该一个或多个缓冲膜的第一阻挡膜，耦合到第一所述多栅极鳍片包括源极区域，漏极区域和多栅极器件的沟道区域，其中所述沟道区域设置在所述源极区域和所述漏极区域之间，间隔膜耦合到所述多栅极器件，栅极鳍片以及耦合到间隔膜的掺杂膜。

115. 发明授权

US08278687B2 Semiconductor heterostructures to reduce short channel effects 有权
标题翻译：半导体异质结构减少短路效应
公开(公告)号：US08278687B2
公开(公告)日：2012-10-02
申请号：US12058101
申请日：2008-03-28
申请人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
发明人： Ravi Pillarisetty , Mantu K. Hudait , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Robert S. Chau
IPC分类号： H01L29/778
CPC分类号： H01L29/7783 , H01L29/42316 , H01L29/7784
摘要： Semiconductor heterostructures to reduce short channel effects are generally described. In one example, an apparatus includes a semiconductor substrate, one or more buffer layers coupled to the semiconductor substrate, a first barrier layer coupled to the one or more buffer layers, a back gate layer coupled to the first barrier layer wherein the back gate layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the back gate layer having a first bandgap, a second barrier layer coupled to the back gate layer wherein the second barrier layer includes a group III-V semiconductor material, a group II-VI semiconductor material, or combinations thereof, the second barrier layer having a second bandgap that is relatively larger than the first bandgap, and a quantum well channel coupled to the second barrier layer, the quantum well channel having a third bandgap that is relatively smaller than the second bandgap.
摘要翻译：通常描述用于减少短通道效应的半导体异质结构。在一个示例中，设备包括半导体衬底，耦合到半导体衬底的一个或多个缓冲层，耦合到一个或多个缓冲层的第一势垒层，耦合到第一阻挡层的背栅层，其中背栅层包括III-V族半导体材料，II-VI族半导体材料或其组合，所述背栅层具有第一带隙，耦合到所述背栅层的第二阻挡层，其中所述第二阻挡层包括III- V族半导体材料，II-VI族半导体材料或其组合，所述第二阻挡层具有相对大于所述第一带隙的第二带隙，以及耦合到所述第二阻挡层的量子阱沟道，所述量子阱沟道具有相对小于第二带隙的第三带隙。

116. 发明申请

US20120231596A1 QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS 有权
标题翻译：具有由金属源/排水源引起的不均匀应变的QUANTUM WELL MOSFET通道，以及合适的反应源/漏极
公开(公告)号：US20120231596A1
公开(公告)日：2012-09-13
申请号：US13479121
申请日：2012-05-23
申请人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
发明人： Prashant Majhi , Mantu K. Hudait , Jack T. Kavalieros , Ravi Pillarisetty , Marko Radosavljevic , Gilbert Dewey , Titash Rakshit , Willman Tsai
IPC分类号： H01L21/335
CPC分类号： H01L29/66431 , H01L21/28518 , H01L21/76802 , H01L21/76805 , H01L21/76897 , H01L29/152 , H01L29/165 , H01L29/41766 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7848 , H01L29/802
摘要： Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
摘要翻译：所描述的实施例包括具有金属源/漏极的应变晶体管量子阱（QW）沟道区，以及保形再生长源/漏极，以在MOS沟道区中赋予单轴应变。沟道层的去除部分可以填充具有不同于沟道材料的晶格间隔的结合材料，以在通道中引起单轴应变，以及在沟道层中引起的双轴应变顶部阻挡层和量子阱的底部缓冲层。

117. 发明授权

US08258543B2 Quantum-well-based semiconductor devices 有权
标题翻译：量子阱半导体器件
公开(公告)号：US08258543B2
公开(公告)日：2012-09-04
申请号：US12632498
申请日：2009-12-07
申请人： Gilbert Dewey , Marko Radosavljevic , Ravi Pillarisetty , Robert S. Chau , Matthew V. Metz
发明人： Gilbert Dewey , Marko Radosavljevic , Ravi Pillarisetty , Robert S. Chau , Matthew V. Metz
IPC分类号： H01L29/66
CPC分类号： H01L29/66666 , H01L29/2003 , H01L29/4236 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
摘要翻译：描述了基于量子阱的半导体器件和形成量子阱基半导体器件的方法。一种方法包括提供设置在衬底上方并包括量子阱沟道区的异质结构。该方法还包括在量子阱沟道区上方形成源极和漏极材料区域。该方法还包括在源极和漏极材料区域中形成沟槽以提供与漏极区域分离的源极区域。该方法还包括在沟槽中，在源极和漏极区之间形成栅极电介质层; 以及在所述沟槽中形成栅电极，在所述栅介质层上方。

118. 发明申请

US20120153387A1 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 有权
标题翻译：具有高浓度的硼氢化锗的晶体管
公开(公告)号：US20120153387A1
公开(公告)日：2012-06-21
申请号：US12975278
申请日：2010-12-21
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

119. 发明授权

US08088665B2 Method of forming self-aligned low resistance contact layer 有权
标题翻译：形成自对准低电阻接触层的方法
公开(公告)号：US08088665B2
公开(公告)日：2012-01-03
申请号：US12228386
申请日：2008-08-11
申请人： Willy Rachmady , Jason W. Klaus , Ravi Pillarisetty , Niloy Mukherjee , Jack Kavalieros , Sean King
发明人： Willy Rachmady , Jason W. Klaus , Ravi Pillarisetty , Niloy Mukherjee , Jack Kavalieros , Sean King
IPC分类号： H01L21/336
CPC分类号： H01L29/41775 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/02636 , H01L21/28518 , H01L21/28525 , H01L21/28556 , H01L29/41783
摘要： Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.
摘要翻译：本发明的实施例描述了在半导体器件上制造低电阻接触层的方法。半导体器件包括具有源区和漏区的衬底。将基板交替地暴露于第一前体和第二前体，以将非晶半导体层选择性地沉积到源极和漏极区域中的每一个上。然后在每个源极和漏极区域上的非晶半导体层上沉积金属层。然后在衬底上进行退火处理，以允许金属层与非晶半导体层反应，以在源极和漏极区域中的每一个上形成低电阻接触层。根据所使用的前体的类型，源极和漏极区域中的每一个上的低电阻接触层可以形成为硅化物层或锗化物层。

120. 发明申请

US20110211402A1 LOW POWER FLOATING BODY MEMORY CELL BASED ON LOW-BANDGAP-MATERIAL QUANTUM WELL 有权
标题翻译：低功率浮动体存储单元，基于低带隙材料量子阱
公开(公告)号：US20110211402A1
公开(公告)日：2011-09-01
申请号：US13069333
申请日：2011-03-22
申请人： Titash Rakshit , Gilbert Dewey , Ravi Pillarisetty
发明人： Titash Rakshit , Gilbert Dewey , Ravi Pillarisetty
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L29/205 , H01L29/7841
摘要： Embodiments of the invention relate to apparatus, system and method for use of a memory cell having improved power consumption characteristics, using a low-bandgap material quantum well structure together with a floating body cell.
摘要翻译：本发明的实施例涉及使用具有改进的功耗特性的存储单元的装置，系统和方法，其与浮体单元一起使用低带隙材料量子阱结构。

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