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111. 发明申请

US20080246080A1 Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS) 审中-公开
标题翻译：基于横沟扩散金属氧化物半导体（LDMOS）的浅沟槽隔离（STI）
公开(公告)号：US20080246080A1
公开(公告)日：2008-10-09
申请号：US12155628
申请日：2008-06-06
申请人： Akira Ito , Henry Kuo-Shun Chen
发明人： Akira Ito , Henry Kuo-Shun Chen
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/086 , H01L29/0865 , H01L29/1083 , H01L29/456 , H01L29/66659
摘要： An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device further includes a shallow trench isolation (STI) region to increase the resistance from the drain region to the source region. The STI region includes a first side vertically aligned with a second side of the gate region. The STI region extends from the first side to a second side in contact with a second side of the drain region. The breakdown voltage of the n-type semiconductor device is directly proportional to a vertical length, or a depth, of the first side and/or the second side of the STI region. The horizontal length, or distance from the first side to the second side, of the STI region does not substantially contribute to the breakdown voltage of the semiconductor device. As a result, a conventional CMOS logic foundry technology may fabricate the STI region of the semiconductor device using a low operating voltage process minimum design rule.
摘要翻译：公开了一种用于增加半导体器件的击穿电压的装置。半导体器件包括表示源极区的第一重掺杂区域。第二重掺杂区域表示半导体器件的漏极区域。第三重掺杂区域表示半导体器件的栅极区域。半导体器件还包括浅沟槽隔离（STI）区域，以增加从漏区到源极区的电阻。 STI区域包括与栅极区域的第二侧垂直对准的第一侧面。 STI区从第一侧延伸到与漏区的第二侧接触的第二侧。 n型半导体器件的击穿电压与STI区域的第一侧和/或第二面的垂直长度或深度成正比。 STI区域的水平长度或从第一侧到第二侧的距离基本上不会有助于半导体器件的击穿电压。结果，传统的CMOS逻辑铸造技术可以使用低工作电压工艺最小设计规则来制造半导体器件的STI区域。

112. 发明申请

US20080217409A1 RFID tag communicating apparatus 审中-公开
标题翻译： RFID标签通信装置
公开(公告)号：US20080217409A1
公开(公告)日：2008-09-11
申请号：US11894825
申请日：2007-08-22
申请人： Akira Ito , Tsuyoshi Ohashi , Kazunari Taki , Osamu Nishikawa , Yasuhisa Ichikawa , Shiro Yamada
发明人： Akira Ito , Tsuyoshi Ohashi , Kazunari Taki , Osamu Nishikawa , Yasuhisa Ichikawa , Shiro Yamada
IPC分类号： G06K7/08 , G06K7/10
CPC分类号： G06K7/10336 , G06K7/0004 , G06K7/10881
摘要： Article can be managed relatively inexpensively without using an expensive database or communication infrastructure. An RFID tag communicating apparatus has an antenna that transmits/receives a signal by wireless communication with RFID circuit elements provided at the tag labels provided at a bookshelf on which books are placed and an operator, respectively, a radio frequency circuit, a barcode reader that optically detects information of a barcode provided at a book; and a control circuit. The control circuit has a function to write various work information of the book in an IC circuit part of the RFID circuit element provided for management of the book via the antenna and the radio frequency circuit in accordance with a detection result of the barcode information by the barcode reader.
摘要翻译：可以在不使用昂贵的数据库或通信基础设施的情况下相对便宜地管理文章。 RFID标签通信装置具有通过无线通信与提供在放置有书籍的书架上的标签标签处的RFID电路元件和操作者分别发送/接收信号的天线，射频电路，条形码读取器光学地检测在书上提供的条形码的信息; 和控制电路。该控制电路具有通过天线和射频电路根据条形码信息的检测结果，将书本的各种作业信息写入设置用于管理书籍的RFID电路元件的IC电路部分的功能条码读取器。

113. 发明申请

US20080130804A1 Interference power estimating device and interference power estimating method 有权
标题翻译：干扰功率估计装置和干扰功率估计方法
公开(公告)号：US20080130804A1
公开(公告)日：2008-06-05
申请号：US11984258
申请日：2007-11-15
申请人： Akira Ito
发明人： Akira Ito
IPC分类号： H04B1/10
CPC分类号： H04B17/26 , H04B17/345 , H04L1/0003 , H04L5/0048 , H04L25/067 , H04L27/0008
摘要： The present invention relates to an interference power estimating device that estimates interference power with high accuracy. The interference power estimating device includes a reference symbol acquiring unit acquiring a reference symbol corresponding to each of the pilot symbols included in a received signal by symbol-averaging a reference signal including the pilot symbol being allocated in positions near in terms of time to each of the pilot symbols and having the number less than the number of the pilot symbols within one slot, and an estimating unit estimating interference power of the received signal by power-valuing each difference between each of the pilot symbols and the reference symbol corresponding to each of the pilot symbols acquired by the reference symbol acquiring unit.
摘要翻译：本发明涉及以高精度估计干扰功率的干扰功率估计装置。干扰功率估计装置包括：参考符号获取单元，通过对包括导频符号的参考信号进行符号平均，获取与包含在接收信号中的每个导频符号相对应的参考符号，所述参考信号被分配在每个所述导频符号并且具有小于一个时隙内的导频符号的数量的数量，以及估计单元，通过对每个导频符号和对应于每个导频符号的参考符号之间的每个差异进行功率估值来估计接收信号的干扰功率由参考符号获取单元获取的导频符号。

114. 发明申请

US20080038034A1 Tape Printer and Tape Cassette 失效
标题翻译：磁带打印机和磁带盒
公开(公告)号：US20080038034A1
公开(公告)日：2008-02-14
申请号：US11663686
申请日：2005-09-26
申请人： Koshiro Yamaguchi , Akira Ito , Yoshio Kunieda , Takahiro Miwa
发明人： Koshiro Yamaguchi , Akira Ito , Yoshio Kunieda , Takahiro Miwa
IPC分类号： B41J11/44
CPC分类号： B41J15/044 , B41J3/4075
摘要： The CPU 81 of the tape printer 1, when the tape printer 1 is turned on, reads the “model name” and the power supply type of “drive power supply” corresponding to each “model name” of the parameter table 131 from the wireless tag circuit element 25 provided in the tape cassette 21 via the R/W module 93, and next, displays on the LCD 7 a request for selecting the model name and the drive power supply of the tape printer and wait for a selection of the model name and the drive power supply. Then, the CPU 81 reads the print control parameters corresponding to the selected model name and the drive power supply from the wireless tag circuit element 25 via the R/W module 93. If the print control parameter read from the wireless tag circuit element 25 is not stored in the ROM 83 or the EEPROM 84, the CPU 81 stores the print control parameter and executes print control based on the print control parameter (S1 to S9).
摘要翻译：带式打印机1的CPU81在带式打印机1打开的同时从无线装置读取与参数表131的各“型号名称”对应的“型号名称”和“驱动电源”的电源类型标签电路元件25，经由R / W模块93设置在带盒21中，接下来，在LCD7上显示选择型号名称和带式打印机的驱动电源的请求，并等待该模型的选择名称和驱动电源。然后，CPU 81经由R / W模块93从无线标签电路元件25读取与所选型号名称对应的打印控制参数和驱动电源。如果从无线标签电路元件25读取的打印控制参数未被存储在ROM 83或EEPROM 84中，则CPU 81存储打印控制参数，并根据打印控制参数执行打印控制（S 1至S 9）。

115. 发明申请

US20070258509A1 Transmission method and transmission apparatus in an OFDM-CDMA communication system 有权
标题翻译： OFDM-CDMA通信系统中的发送方法和发送装置
公开(公告)号：US20070258509A1
公开(公告)日：2007-11-08
申请号：US11822354
申请日：2007-07-05
申请人： Akira Ito , Masahiko Shimizu
发明人： Akira Ito , Masahiko Shimizu
IPC分类号： H04B1/00
CPC分类号： H04L5/0019 , H04L1/0003 , H04L5/006 , H04L25/0216 , H04L25/0228 , H04L27/2646 , H04L27/2647
摘要： A OFDM-CDMA communication system that generates a plurality of subcarrier components by multiplying each of a plurality of transmission symbols by a channelization code whose length is N according to a spreading factor, and transmits those subcarrier components by a plurality of different subcarriers, measures the propagation environment of each subcarrier, divides the subcarriers into groups having N number of subcarriers in each group whose propagation environments are close one another, and transmits the N number of subcarrier components, which have been multiplied by the channelization code, by subcarriers of the same group.
摘要翻译：一种OFDM-CDMA通信系统，其通过将多个发送符号中的每一个乘以根据扩展因子的长度为N的信道化码来生成多个子载波分量，并且通过多个不同的子载波来发送这些子载波分量，每个子载波的传播环境在每个传播环境彼此接近的组中将子载波划分成具有N个子载波的组，并且将与信道化码相乘的N个子载波分量相乘，组。

116. 发明申请

US20070108524A1 Low threshold voltage PMOS apparatus and method of fabricating the same 有权
标题翻译：低阈值电压PMOS器件及其制造方法
公开(公告)号：US20070108524A1
公开(公告)日：2007-05-17
申请号：US11648651
申请日：2007-01-03
申请人： Akira Ito , Henry Chen
发明人： Akira Ito , Henry Chen
IPC分类号： H01L27/12
CPC分类号： H01L29/1083 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： A P-type metal oxide semiconductor (PMOS) device can include an N-well that does not extend completely throughout the active region of the PMOS device. For example, the PMOS device can be fabricated using a masking step to provide an N-well having an inner perimeter and an outer perimeter. The inner perimeter of the N-well surrounds at least a portion of the active region of the PMOS device. According to an embodiment, the inner perimeter of the N-well surrounds the entire active region. The PMOS device can include a deep N-well in contact with the N-well.
摘要翻译： P型金属氧化物半导体（PMOS）器件可以包括不在PMOS器件的整个有源区域完全延伸的N阱。例如，可以使用掩模步骤制造PMOS器件，以提供具有内周长和外周长的N阱。 N阱的内周围包围PMOS器件的有源区的至少一部分。根据实施例，N阱的内周围围绕整个有源区。 PMOS器件可以包括与N阱接触的深N阱。

117. 发明授权

US07211843B2 System and method for programming a memory cell 有权
标题翻译：用于编程存储器单元的系统和方法
公开(公告)号：US07211843B2
公开(公告)日：2007-05-01
申请号：US10355260
申请日：2003-01-31
申请人： Khim L. Low , Todd L. Brooks , Agnes Woo , Akira Ito
发明人： Khim L. Low , Todd L. Brooks , Agnes Woo , Akira Ito
IPC分类号： H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.
摘要翻译：本发明涉及用于编程存储器单元的系统和方法。更具体地说，本发明涉及在受控时间段内对存储器单元的电流的受控应用。本发明利用具有第一晶体管和第二晶体管的电流镜配置，其中第二晶体管耦合到存储单元。存储单元的编程包括向第一晶体管施加电压，由此在第一晶体管中产生第一电流。第二晶体管的栅极耦合到第一晶体管，由此在第二晶体管中产生第二电流。第二电流与第一电流成比例。第二电流被提供给存储器单元，由此第二电流对存储单元进行编程。

118. 发明申请

US20060203424A1 High density maze capacitor 有权
公开(公告)号：US20060203424A1
公开(公告)日：2006-09-14
申请号：US11324221
申请日：2006-01-04
申请人： Henry Chen , Akira Ito
发明人： Henry Chen , Akira Ito
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01G4/228 , H01G4/38 , H01L27/0207 , H01L27/0805 , H01L2924/0002 , Y10T29/43 , H01L2924/00
摘要： A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second arm, and a via. The first arm has a first end and a second end. The second arm has a third end and a fourth end. The first arm and the second arm intersect and the first, second, third and fourth ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the first and second arms.

119. 发明申请

US20060121606A1 Cell culture method and cultured tissue 审中-公开
标题翻译：细胞培养法和培养组织
公开(公告)号：US20060121606A1
公开(公告)日：2006-06-08
申请号：US11271911
申请日：2005-11-14
申请人： Akira Ito , Hiroyuki Honda , Takeshi Kobayashi , Minoru Ueda , Hideaki Kagami , Ken-ichiro Hata
发明人： Akira Ito , Hiroyuki Honda , Takeshi Kobayashi , Minoru Ueda , Hideaki Kagami , Ken-ichiro Hata
IPC分类号： C12N5/06
CPC分类号： C12N5/0062
摘要： A cell culture method prepares first cells that are adhesion-dependent cells and monolayered or multilayered cells on a culture surface of a culture substrate, seeds second cells that are adhesion-dependent cells and are magnetized by allowing to have magnetic particles on the first cells, induces the second cells to a predetermined position on the first cells by magnetic force, and cultures the first cells and the second cells in a cell arrangement obtained by the magnetic induction. According to this cell culture method, after a cell sheet was prepared individually, cells can be multilayered without changing a temperature, peeling the monolayered sheet and laminating the monolayered sheets.
摘要翻译：细胞培养方法在培养基底的培养表面上制备作为粘附依赖性细胞和单层或多层细胞的第一细胞，作为粘附依赖性细胞的种子第二细胞并通过在第一细胞上具有磁性颗粒而被磁化，通过磁力将第二细胞诱导到第一细胞上的预定位置，并以通过磁感应获得的细胞排列来培养第一细胞和第二细胞。根据该细胞培养方法，单独制备细胞片后，细胞可以多层而不改变温度，剥离单层片材并层压单层片材。

120. 发明授权

US07009832B1 High density metal-to-metal maze capacitor with optimized capacitance matching 失效
标题翻译：高密度金属对金属迷宫电容器，具有优化的电容匹配
公开(公告)号：US07009832B1
公开(公告)日：2006-03-07
申请号：US11078511
申请日：2005-03-14
申请人： Henry KuoShun Chen , Akira Ito
发明人： Henry KuoShun Chen , Akira Ito
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01G4/228 , H01G4/38 , H01L27/0207 , H01L27/0805 , H01L2924/0002 , Y10T29/43 , H01L2924/00
摘要： A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a transverse arm, and a via. The upright arm has a top end and a bottom end that extend at substantially right angles to a central axis of the upright arm. The transverse arm has a left and right end that extend at substantially right angles to a central axis of the transverse arm. The upright arm and the transverse arm intersect to form a cross-like pattern and the top, bottom, left and right ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the upright and transverse arms.
摘要翻译：一种包括设置在基板上的第一和第二分量电容器结构的电容器。元件电容器结构包括直立臂，横向臂和通路。直立臂具有与直立臂的中心轴线基本成直角延伸的顶端和底端。横臂具有与横臂的中心轴线基本成直角延伸的左端和右端。直立臂和横臂相交以形成十字形图案，并且顶部，底部，左端和右端都沿相同的旋转方向延伸。通孔电连接到直立臂和横向臂的交叉区域。

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