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111. 发明授权

US06518628B1 Integrated CMOS circuit configuration, and production of same 有权
标题翻译：集成CMOS电路配置，生产相同
公开(公告)号：US06518628B1
公开(公告)日：2003-02-11
申请号：US09423864
申请日：1999-11-15
申请人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
发明人： Wolfgang Krautschneider , Franz Hofmann , Lothar Risch
IPC分类号： H01L2976
CPC分类号： H01L27/0922
摘要： An integrated CMOS circuit arrangement and a method of manufacturing same, which includes both a first MOS transistor and a second MOS transistor complementary thereto, wherein one of the MOS transistors is arranged at the floor of a trench and the other is arranged at the principal surface of a semiconductor substrate. The MOS transistors are arranged relative to one another such that a current flow through the MOS transistors respectively occurs substantially parallel to a sidewall of the trench that is arranged between the MOS transistors.
摘要翻译：一种集成CMOS电路装置及其制造方法，其包括第一MOS晶体管和与其互补的第二MOS晶体管，其中MOS晶体管中的一个布置在沟槽的底部，而另一个布置在主表面的半导体衬底。 MOS晶体管相对于彼此布置，使得流过MOS晶体管的电流分别基本上平行于布置在MOS晶体管之间的沟槽的侧壁。

112. 发明授权

US06352894B1 Method of forming DRAM cell arrangement 有权
标题翻译：形成DRAM单元布置的方法
公开(公告)号：US06352894B1
公开(公告)日：2002-03-05
申请号：US09482064
申请日：2000-01-13
申请人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
发明人： Bernd Goebel , Wolfgang Roesner , Franz Hofmann , Emmerich Bertagnolli , Eve Marie Martin
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823 , Y10S257/906 , Y10S438/947
摘要： A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F2, F being the minimal structural size that can be produced in the respective technology.
摘要翻译：存储单元具有排列成行和列的半导体衬底的多个突起，相邻的一列突起相对于平行于列延伸的y轴平移对称。每个突起具有选择晶体管的至少一个第一源极/漏极区域和布置在第一源极/漏极区域下方的一个沟道区域，其被环形的栅极电极包围。存储电容器连接在第一源极/漏极区域和位线之间。位线以及存储电容器基本上布置在半导体衬底的上方。选择晶体管的第二源极/漏极区域被埋在半导体衬底中并彼此连接。字线可以形成为相邻栅电极的形式自对称。可以通过仅使用一个掩模的蚀刻来产生突起。可以生产具有4F2面积的存储单元，F是可以在各自技术中生产的最小结构尺寸。

113. 发明授权

US06255684B1 DRAM cell configuration and method for its production 失效
标题翻译： DRAM单元配置及其生产方法
公开(公告)号：US06255684B1
公开(公告)日：2001-07-03
申请号：US09071798
申请日：1998-05-04
申请人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
发明人： Wolfgang Roesner , Lothar Risch , Franz Hofmann
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A DRAM cell configuration includes a vertical MOS transistor per memory cell. First source/drain regions of the transistor each belong to two adjacent transistors and adjoin a bit line. Second source/drain regions of the transistor are connected to a storage node. A gate electrode of the transistor has exactly two sides adjoined by a gate oxide. The DRAM cell configuration can be produced by using three masks, with a memory cell area of 4 F2. F is a minimum structure size which can be produced by using the respective technology.
摘要翻译： DRAM单元配置包括每个存储单元的垂直MOS晶体管。晶体管的第一源极/漏极区域分别属于两个相邻的晶体管并与位线相邻。晶体管的第二源/漏区连接到存储节点。晶体管的栅电极具有由栅极氧化物邻接的正好两侧。可以通过使用具有4F2的存储单元面积的三个掩模来产生DRAM单元配置。 F是可以通过使用各自技术制造的最小结构尺寸。

114. 发明授权

US6125050A Configuration for driving parallel lines in a memory cell configuration 有权
标题翻译：用于驱动存储单元配置中的并行线的配置
公开(公告)号：US6125050A
公开(公告)日：2000-09-26
申请号：US335365
申请日：1999-06-17
申请人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
发明人： Franz Hofmann , Josef Willer , Hans Reisinger , Paul-Werner Basse , Wolfgang Krautschneider
IPC分类号： H01L27/112 , G11C5/02 , H01L21/8246
CPC分类号： H01L27/0207 , H01L27/1126 , H01L27/11293 , H01L27/11803
摘要： Parallel lines, for example bit lines in a memory cell configuration formed of doped regions in a semiconductor substrate, are driven by electrically connecting a number of the lines to one another and to a common node. A number of selection lines extend transversely to the lines. MOS transistors are arranged at the points of intersection and are connected in series along one of the lines. The gate electrode of the MOS transistors is formed by the corresponding selection line. At least one MOS transistor in each of the parallel lines has a higher threshold voltage than the others.
摘要翻译：平行线，例如由半导体衬底中的掺杂区形成的存储单元配置中的位线，通过将多个线彼此电连接并连接到公共节点来驱动。多条选择线横向延伸。 MOS晶体管布置在交点处，并沿着一条线串联连接。 MOS晶体管的栅电极由相应的选择线形成。每条并行线路中的至少一个MOS晶体管的阈值电压高于其他。

115. 发明授权

US6037209A Method for producing a DRAM cellular arrangement 有权
标题翻译：用于制造DRAM蜂窝装置的方法
公开(公告)号：US6037209A
公开(公告)日：2000-03-14
申请号：US254696
申请日：1999-03-15
申请人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
发明人： Wolfgang Rosner , Lothar Risch , Franz Hofmann , Reinhard Stengl
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.
摘要翻译： PCT No.PCT / DE97 / 01580 Sec。 371 1999年3月15日 102（e）1999年3月15日PCT 1997年7月28日PCT公布。出版物WO98 / 11604 日期1998年3月19日DRAM单元布置包括每个存储单元的垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储节点，其沟道区域（3）被栅电极环形封闭 13），并且其第二源极/漏极区域连接到掩埋位线。借助于间隔器技术，仅使用两个掩模来制造DRAM单元布置，存储单元面积为2F2，其中F是可以使用各自技术产生的最小结构尺寸。

116. 发明授权

US08067249B2 Method for functionalizing biosensor chips 有权
标题翻译：功能化生物传感器芯片的方法
公开(公告)号：US08067249B2
公开(公告)日：2011-11-29
申请号：US11587058
申请日：2005-03-18
申请人： Alexander Frey , Franz Hofmann , Petra Schindler-Bauer
发明人： Alexander Frey , Franz Hofmann , Petra Schindler-Bauer
IPC分类号： H01L21/00
CPC分类号： G01N33/54366 , G01N27/3277
摘要： A method is disclosed for functionalizing biosensors. The biosensors are based on semiconductor chips mounted on a finished processed wafer. They are provided with sensor fields placed thereupon, which are arranged in any array, and, to be precise, for carrying out a functionalization, for example, with organic molecules such as nucleic acids like DNA, RNA and PNA or with their derivatives, proteins, sugar molecules, or antibodies.
摘要翻译：公开了用于使生物传感器功能化的方法。生物传感器基于安装在成品加工晶片上的半导体芯片。它们设置有放置在其上的传感器场，其被布置成任何阵列，并且准确地，用于进行功能化，例如用有机分子例如核酸如DNA，RNA和PNA或其衍生物，蛋白质，糖分子或抗体。

117. 发明授权

US07838925B2 Integrated circuit including a vertical transistor and method 有权
标题翻译：集成电路包括垂直晶体管和方法
公开(公告)号：US07838925B2
公开(公告)日：2010-11-23
申请号：US12173524
申请日：2008-07-15
申请人： Wolfgang Roesner , Franz Hofmann
发明人： Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/732
CPC分类号： H01L29/7827 , H01L21/2255 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/0878 , H01L29/0886 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/66734 , H01L29/7813
摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.
摘要翻译：一种包括垂直晶体管和制造方法的集成电路。在一个实施例中，垂直晶体管形成在半导体衬底的柱中。埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。第二绝缘层布置在接触结构的上方并与之相邻。第一和第二绝缘层中的至少一个包括掺杂剂。掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

118. 发明授权

US07772580B2 Integrated circuit having a cell with a resistivity changing layer 有权
标题翻译：具有具有电阻率变化层的单元的集成电路
公开(公告)号：US07772580B2
公开(公告)日：2010-08-10
申请号：US11837380
申请日：2007-08-10
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L29/02
CPC分类号： H01L45/149 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/065 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/1683
摘要： In an embodiment of the invention, an integrated circuit having a cell is provided. The cell may include a field effect transistor structure which includes a gate stack and a resistivity changing material structure disposed above the gate stack, wherein the resistivity changing material structure includes a resistivity changing material which is configured to change its resistivity in response to the application of an electrical voltage to the resistivity changing material structure.
摘要翻译：在本发明的实施例中，提供了具有单元的集成电路。电池可以包括场效应晶体管结构，其包括设置在栅极堆叠上方的栅极堆叠和电阻率变化材料结构，其中电阻率变化材料结构包括电阻率变化材料，其被配置为响应于应用对电阻率变化材料结构的电压。

119. 发明申请

US20100013005A1 INTEGRATED CIRCUIT INCLUDING A VERTICAL TRANSISTOR AND METHOD 有权
标题翻译：集成电路，包括垂直晶体管和方法
公开(公告)号：US20100013005A1
公开(公告)日：2010-01-21
申请号：US12173524
申请日：2008-07-15
申请人： Wolfgang Roesner , Franz Hofmann
发明人： Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/2255 , H01L27/108 , H01L27/10802 , H01L27/10876 , H01L29/0878 , H01L29/0886 , H01L29/1083 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/66734 , H01L29/7813
摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.
摘要翻译：一种包括垂直晶体管和制造方法的集成电路。在一个实施例中，垂直晶体管形成在半导体衬底的柱中。埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。第二绝缘层布置在接触结构的上方并与之相邻。第一和第二绝缘层中的至少一个包括掺杂剂。掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

120. 发明授权

US07400695B2 System and method for time-marking data 失效
标题翻译：时间标记数据的系统和方法
公开(公告)号：US07400695B2
公开(公告)日：2008-07-15
申请号：US10474951
申请日：2002-04-08
申请人： Daniel Murdin , Predrag Pucar , Franz Hofmann
发明人： Daniel Murdin , Predrag Pucar , Franz Hofmann
IPC分类号： H04J3/06
CPC分类号： G06F1/14
摘要： This invention concerns a system comprising processors (2, 3) arranged so as to receive and process data arriving at the system and containing time-indicating means (11, 17, 21) operatively connected to said processors and arranged so as to furnish time data to the processors for time-marking of the data. The time-indicating means (11, 17, 21) include a hardware clock arranged so as to generate a clock signal, and further arranged so as to receive second time data from at least one additional time reference and modify the clock signal from the hardware clock using the second time data in order to generate the first time data. The time-indicating means (11, 17, 21) are arranged so as to add to the clock signal, during the generation of the first time data, a compensation signal (δτi) based on said second time data. The invention also concerns a method for time-marking data.
摘要翻译：本发明涉及一种系统，包括处理器（2,3），其被布置为接收和处理到达系统的数据，并且包含可操作地连接到所述处理器的时间指示装置（11,17,21），并被布置成提供时间数据对处理器进行数据的时间标记。时间指示装置（11,17,21）包括布置成产生时钟信号的硬件时钟，并且还被布置为从至少一个附加时间基准接收第二时间数据，并修改来自硬件的时钟信号时钟使用第二次数据，以生成第一次数据。时间指示装置（11,17,21）被布置为在第一时间数据的生成期间增加基于所述第二时间数据的补偿信号（deltataui）的时钟信号。本发明还涉及用于对数据进行时间标记的方法。

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