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111. 发明授权

US07812387B2 Trench capacitor 有权
标题翻译：沟槽电容器
公开(公告)号：US07812387B2
公开(公告)日：2010-10-12
申请号：US12062310
申请日：2008-04-03
申请人： Kangguo Cheng
发明人： Kangguo Cheng
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/66181 , A01N25/08 , A01N25/12 , A01N59/00 , A01N59/06 , A01N59/20 , A01N2300/00
摘要： A trench capacitor with an isolation collar in a semiconductor substrate where the substrate adjacent to the isolation collar is free of dopants caused by auto-doping. The method of fabricating the trench capacitor includes the steps of forming a trench in the semiconductor substrate; depositing a dielectric layer on a sidewall of the trench; filling the trench with a first layer of undoped polysilicon; etching away the first layer of undoped polysilicon and the dielectric layer from an upper section of the trench whereby the semiconductor substrate is exposed at the sidewall in the upper section of the trench; forming an isolation collar layer on the sidewall in the upper section of the trench; and filling the trench with a second layer of doped polysilicon.
摘要翻译：在半导体衬底中具有隔离环的沟槽电容器，其中邻近隔离环的衬底没有由自掺杂引起的掺杂剂。制造沟槽电容器的方法包括在半导体衬底中形成沟槽的步骤; 在沟槽的侧壁上沉积介电层; 用第一层未掺杂的多晶硅填充沟槽; 从沟槽的上部蚀刻掉未掺杂的多晶硅和介电层的第一层，由此半导体衬底在沟槽的上部的侧壁处暴露; 在沟槽的上部的侧壁上形成隔离套环层; 并用第二层掺杂多晶硅填充沟槽。

112. 发明授权

US07791124B2 SOI deep trench capacitor employing a non-conformal inner spacer 失效
标题翻译： SOI深沟槽电容器采用非保形内隔板
公开(公告)号：US07791124B2
公开(公告)日：2010-09-07
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

113. 发明授权

US07785979B2 Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same 有权
标题翻译：包括具有不同薄片电阻的电阻器的集成电路及其制造方法
公开(公告)号：US07785979B2
公开(公告)日：2010-08-31
申请号：US12173407
申请日：2008-07-15
申请人： Roger Allen Booth, Jr. , Kangguo Cheng , Terence B. Hook
发明人： Roger Allen Booth, Jr. , Kangguo Cheng , Terence B. Hook
IPC分类号： H01L21/324 , H01L21/8238
CPC分类号： H01L27/0629 , H01L28/20
摘要： The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.
摘要翻译：本文公开了包括具有相同结构但具有不同薄层电阻的电阻器的集成电路的制造。在一个实施例中，一种制造集成电路的方法包括：与半导体衬底之上或之内的第二电阻器横向隔开的第一电阻器同时形成，所述第一和第二电阻器包括掺杂的半导体材料; 在第一和第二电阻器和半导体衬底上沉积掺杂剂接收材料; 在所述第一电阻器上移除所述掺杂剂接收材料，同时将所述掺杂剂接收材料保持在所述第二电阻器上; 以及使所述第一和第二电阻器退火以使所述第一电阻器的第一薄层电阻与所述第二电阻器的第二薄层电阻不同。

114. 发明授权

US07776706B2 Forming SOI trench memory with single-sided buried strap 失效
标题翻译：形成具有单面埋地带的SOI沟槽存储器
公开(公告)号：US07776706B2
公开(公告)日：2010-08-17
申请号：US12169727
申请日：2008-07-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/8234
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

115. 发明申请

US20100203732A1 FIN AND FINFET FORMATION BY ANGLED ION IMPLANTATION 有权
标题翻译：通过离子植入形成的FIN和FINFET
公开(公告)号：US20100203732A1
公开(公告)日：2010-08-12
申请号：US12368561
申请日：2009-02-10
申请人： Bruce B. Doris , Kangguo Cheng , Geng Wang
发明人： Bruce B. Doris , Kangguo Cheng , Geng Wang
IPC分类号： H01L21/302 , H01L21/30 , H01L21/308
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/26586 , H01L21/3086 , H01L21/3088 , H01L21/32134 , H01L21/32135 , H01L29/66795 , Y10S438/942 , Y10S438/947
摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.
摘要翻译：通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。然后在半导体含有层顶上形成具有多个开口的掩模，其中掩模的多个开口中的相邻开口被最小特征尺寸分开。此后，进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分，其中基本上不含掺杂剂的剩余部分存在于掩模下方。含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分，以提供亚光刻尺寸的图案，并且将图案转移到衬底中以提供翅片结构的亚光刻尺寸。

116. 发明申请

US20100200949A1 METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE 审中-公开
标题翻译：用于调节金属栅极和高K器件的阈值电压的方法
公开(公告)号：US20100200949A1
公开(公告)日：2010-08-12
申请号：US12370024
申请日：2009-02-12
申请人： Roger A. Booth, JR. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
发明人： Roger A. Booth, JR. , Kangguo Cheng , Robert Hannon , Ravi M. Todi , Geng Wang
IPC分类号： H01L29/94 , H01L21/334
CPC分类号： H01L29/945 , H01L27/0605 , H01L27/0733 , H01L27/1203 , H01L28/90 , H01L29/66181
摘要： A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.
摘要翻译：形成深沟槽电容器的方法包括提供晶片。器件形成在晶片的前侧。在晶片的基板上形成贯通硅通孔。深沟槽形成在晶片的背面。在深沟槽中形成深沟槽电容器。直通硅通孔将深沟槽电容器连接到器件。

117. 发明授权

US07759188B2 Method of fabricating vertical body-contacted SOI transistor 失效
标题翻译：垂直体接触SOI晶体管的制造方法
公开(公告)号：US07759188B2
公开(公告)日：2010-07-20
申请号：US12002828
申请日：2007-12-19
申请人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Gary B. Bronner , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/66666 , H01L29/78642
摘要： A method of fabricating a vertical field effect transistor (“FET”) is provided which includes a transistor body region and source and drain regions disposed in a single-crystal semiconductor-on-insulator (“SOI”) region of a substrate adjacent a sidewall of a trench. The substrate includes a buried insulator layer underlying the SOI region and a bulk region underlying the buried insulator layer. A buried strap conductively connects the SOI region to a lower node disposed below the SOI region and a body contact extends from the transistor body region to the bulk region of the substrate, the body contact being insulated from the buried strap.
摘要翻译：提供一种制造垂直场效应晶体管（“FET”）的方法，其包括晶体管本体区域和设置在邻近侧壁的衬底的单晶半导体绝缘体（“SOI”）区域中的源极和漏极区域的沟渠衬底包括在SOI区域下面的掩埋绝缘体层和埋在掩埋绝缘体层下面的主体区域。掩埋带导电地将SOI区域连接到设置在SOI区域下方的下部节点，并且主体接触从晶体管本体区域延伸到衬底的主体区域，身体接触部与掩埋带绝缘。

118. 发明授权

US07749835B2 Trench memory with self-aligned strap formed by self-limiting process 失效
标题翻译：沟槽记忆带自行排列的带子，由自限制过程形成
公开(公告)号：US07749835B2
公开(公告)日：2010-07-06
申请号：US12048263
申请日：2008-03-14
申请人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
发明人： Xi Li , Kangguo Cheng , Johnathan Faltermeier
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L29/945 , H01L21/32137 , H01L21/76232 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.
摘要翻译：描述半导体结构。该结构包括形成在具有绝缘体上半导体（SOI）层和掩埋绝缘（BOX）层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料，所述填充材料在所述沟槽存储单元内形成“V”形，其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。还描述了制造半导体结构的方法。该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层，使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。

119. 发明授权

US07737482B2 Self-aligned strap for embedded trench memory on hybrid orientation substrate 失效
标题翻译：用于混合取向基板上嵌入式沟槽存储器的自对准带
公开(公告)号：US07737482B2
公开(公告)日：2010-06-15
申请号：US11538982
申请日：2006-10-05
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10829 , H01L27/10867 , H01L27/1087 , H01L27/1207 , H01L29/78
摘要： Structures including a self-aligned strap for embedded trench memory (e.g., trench capacitor) on hybrid orientation technology (HOT) substrate, and related method, are disclosed. One structure includes a hybrid orientation substrate including a semiconductor-on-insulator (SOI) section and a bulk semiconductor section; a transistor over the SOI section; a trench capacitor in the bulk semiconductor section; and a self-aligned strap extending from a source/drain region of the transistor to an electrode of the trench capacitor. The method does not require additional masks to generate the strap, results in a self-aligned strap and improved device performance. In one embodiment, the strap is a silicide strap.
摘要翻译：公开了包括用于混合取向技术（HOT）衬底上的嵌入式沟槽存储器（例如，沟槽电容器）的自对准带的结构以及相关方法。一种结构包括：包含绝缘体上半导体（SOI）部分和体半导体部分的混合取向衬底; SOI部分上的晶体管; 体半导体部分中的沟槽电容器; 以及从晶体管的源极/漏极区域延伸到沟槽电容器的电极的自对准带。该方法不需要额外的掩模来生成带，导致自对准带和改进的设备性能。在一个实施例中，带是硅化物带。

120. 发明授权

US07728371B2 SOI CMOS compatible multiplanar capacitor 有权
标题翻译： SOI CMOS兼容多平面电容器
公开(公告)号：US07728371B2
公开(公告)日：2010-06-01
申请号：US11857770
申请日：2007-09-19
申请人： Kangguo Cheng , Louis C Hsu , Jack A. Mandelman , William Tonti
发明人： Kangguo Cheng , Louis C Hsu , Jack A. Mandelman , William Tonti
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L28/60
摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.
摘要翻译：孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。隔离的浅沟槽隔离部分和由导电材料的环限定的掩埋绝缘体层的部分被蚀刻以形成空腔。在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个第二电极。

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