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111. 发明申请

US20060043502A1 Structure and method to fabricate finfet devices 有权
标题翻译：制造finfet设备的结构和方法
公开(公告)号：US20060043502A1
公开(公告)日：2006-03-02
申请号：US11259483
申请日：2005-10-26
申请人： Wesley Natzle , Bruce Doris
发明人： Wesley Natzle , Bruce Doris
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66795
摘要： There is provided a method for fabricating a FinFET in which a self-limiting reaction is employed to produce a unique and useful structure that may be detectable with simple failure analysis techniques. The structure is an improved vertical fin with a gently sloping base portion that is sufficient to reduce or prevent the formation of an undercut area in the base of the vertical fin. The structure is formed via the self-limiting properties of the reaction so that the products of the reaction form both vertically on a surface of the vertical fin and horizontally on a surface of an insulating layer (e.g., buried oxide). The products preferentially accumulate faster at the base of the vertical fin where the products from both the horizontal and vertical surfaces overlap. This accumulation or build-up results from a volume expansion stemming from the reaction. The faster accumulation in the corner areas near the base, limits the reaction first in the base region, thereby etching less material and forming the remaining, un-etched material into the sloping dielectric base.
摘要翻译：提供了一种用于制造FinFET的方法，其中使用自限制反应来产生可用简单的故障分析技术检测的唯一且有用的结构。该结构是一种改进的垂直翅片，其具有缓慢倾斜的基部，其足以减少或防止在垂直翅片的底部中形成底切区域。该结构通过反应的自限制性质形成，使得反应产物在垂直翅片的表面上垂直形成并且在绝缘层（例如，掩埋氧化物）的表面上水平地形成。在水平和垂直表面的产品重叠的情况下，产品优先在垂直翅片的底部积聚得更快。这种积聚或积聚是由反应产生的体积膨胀造成的。在基部附近的角落区域中更快地积聚，首先在基底区域中限制反应，从而蚀刻更少的材料并将剩余的未蚀刻的材料形成到倾斜电介质基底中。

112. 发明申请

US20060001095A1 ULTRA THIN BODY FULLY-DEPLETED SOI MOSFETS 失效
标题翻译：超薄体全绝缘SOI MOSFET
公开(公告)号：US20060001095A1
公开(公告)日：2006-01-05
申请号：US10710273
申请日：2004-06-30
申请人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
发明人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
IPC分类号： H01L29/76 , H01L21/00
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772
摘要： A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.
摘要翻译：提供了一种制造超薄体全耗尽SOI SOI的方法，其中SOI厚度随着栅极长度变化而变化，从而最小化通常由SOI厚度和栅极长度变化引起的阈值电压变化。本发明的方法使用其中注入氮的替代浇口工艺，以便在形成凹陷通道期间选择性地延迟氧化。可以使用自限制化学氧化物去除（COR）处理步骤来改善凹陷通道步骤中的控制。如果沟道被掺杂，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的增加而增加。如果通道是未掺杂或反掺杂的，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的减小而减小。

113. 发明申请

US20050282325A1 Structure and method to improve channel mobility by gate electrode stress modification 审中-公开
公开(公告)号：US20050282325A1
公开(公告)日：2005-12-22
申请号：US11201163
申请日：2005-08-11
申请人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

114. 发明申请

US20050280051A1 Isolation structures for imposing stress patterns 审中-公开
公开(公告)号：US20050280051A1
公开(公告)日：2005-12-22
申请号：US11200958
申请日：2005-08-10
申请人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman
发明人： Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Jack Mandelman
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L29/80 , H01L31/109 , H01L31/112
CPC分类号： H01L29/7846 , H01L21/76232 , H01L21/823807 , H01L21/823878 , H01L29/785
摘要： A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate STI fill material. The STI regions are formed in the substrate layer and impose forces on adjacent substrate areas. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance are achieved.

115. 发明申请

US20050148146A1 High performance strained CMOS devices 失效
标题翻译：高性能应变CMOS器件
公开(公告)号：US20050148146A1
公开(公告)日：2005-07-07
申请号：US11060784
申请日：2005-02-18
申请人： Bruce Doris , Oleg Gluschenkov
发明人： Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L20060101 , H01L21/336 , H01L21/76 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/78 , H01L29/7846
摘要： A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.
摘要翻译：一种半导体器件和制造方法提供一种具有浅沟槽隔离的n沟道场效应晶体管（nFET），其具有在与电流流动方向平行的方向上突出Si-SiO 2界面; 在横向于电流的方向上。器件和方法还提供具有浅沟槽隔离的p沟道场效应晶体管（pFET），其具有在横向于电流的方向上突出Si-SiO 2界面的突出端。然而，pFET的浅沟槽隔离在平行于电流方向的方向上没有突出端。

116. 发明申请

US20050118826A1 Ultra-thin Si MOSFET device structure and method of manufacture 失效
标题翻译：超薄Si MOSFET器件结构及制造方法
公开(公告)号：US20050118826A1
公开(公告)日：2005-06-02
申请号：US10725848
申请日：2003-12-02
申请人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
发明人： Diane Boyd , Bruce Doris , Meikei Ieong , Devendra Sadana
IPC分类号： H01L21/265 , H01L21/28 , H01L21/311 , H01L21/336 , H01L29/10 , H01L29/49 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28194 , H01L21/26533 , H01L21/28202 , H01L29/1083 , H01L29/49 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/78
摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.
摘要翻译：本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

117. 发明申请

US20050106799A1 STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL 失效
标题翻译：具有颗粒半导体材料的应力半导体器件结构
公开(公告)号：US20050106799A1
公开(公告)日：2005-05-19
申请号：US10707018
申请日：2003-11-14
申请人： Bruce Doris , Michael Belyansky , Diane Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Bruce Doris , Michael Belyansky , Diane Boyd , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7845 , H01L21/26513 , H01L21/2658 , H01L21/28035 , H01L21/28167 , H01L21/28247 , H01L21/324 , H01L21/823807 , H01L21/823842 , H01L29/1083 , H01L29/4925 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.
摘要翻译：一种半导体器件结构的制造方法，包括：提供基板，在所述基板上设置电极，在所述电极中形成凹部，所述凹部具有开口，在所述凹部内设置小晶粒半导体材料，覆盖所述开口以容纳小晶粒半导体材料，在凹陷内，然后退火所得结构。

118. 发明申请

US20050093081A1 OXIDATION METHOD FOR ALTERING A FILM STRUCTURE AND CMOS TRANSISTOR STRUCTURE FORMED THEREWITH 失效
标题翻译：用于改造薄膜结构的氧化方法和形成的CMOS晶体管结构
公开(公告)号：US20050093081A1
公开(公告)日：2005-05-05
申请号：US10605889
申请日：2003-11-04
申请人： Michael Belyansky , Diane Boyd , Bruce Doris , Oleg Gluschenkov
发明人： Michael Belyansky , Diane Boyd , Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

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