专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

111. 发明授权

US06734053B2 Effective MIM fabrication method and apparatus to avoid breakdown and leakage on damascene copper process 失效
公开(公告)号：US06734053B2
公开(公告)日：2004-05-11
申请号：US10102255
申请日：2002-03-20
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L218234
CPC分类号： H01L28/40 , H01L27/0805
摘要： A method and apparatus for forming a metal-insulator-metal device that avoids breakdown and leakage due to semiconductor damascene copper fabrication processes associated with the formation of the metal-insulator-metal device. An extra pattern for forming a metal-insulator-metal device can be defined to remove an outer top electrode area associated with the metal-insulator-metal device. The metal-insulator-metal device can be formed without the outer top electrode area to avoid recesses in an insulator layer thereof and achieve a final metal-insulator-metal device structure that avoids breakdown and leakage as a result of associated damascene copper processes.

112. 发明授权

US06562712B2 Multi-step planarizing method for forming a patterned thermally extrudable material layer 有权
公开(公告)号：US06562712B2
公开(公告)日：2003-05-13
申请号：US09898597
申请日：2001-07-03
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76877
摘要： Within a method for forming a patterned microelectronic layer there is first provided a substrate having an aperture formed therein. There is then formed over the substrate and filling the aperture a blanket microelectronic layer. There is then planarized, while employing a first planarizing method, the blanket microelectronic layer to form a once planarized patterned microelectronic layer within the aperture. There is then thermal annealed, while employing a thermal annealing method, the once planarized patterned microelectronic layer within the aperture to form a thermal annealed once planarized patterned microelectronic layer within the aperture. Finally, there is then planarized, while employing a second planarizing method, the thermal annealed once planarized patterned microelectronic layer within the aperture to form a thermal annealed twice planarized patterned microelectronic layer within the aperture. The method is particularly useful for forming, with enhanced integrity, and in particular enhanced physical integrity, such as but not limited to enhanced dimensional integrity, a patterned copper containing microelectronic conductor layer within an aperture within a substrate employed within a microelectronic fabrication.

113. 发明授权

US06395642B1 Method to improve copper process integration 有权
标题翻译：改善铜工艺整合的方法
公开(公告)号：US06395642B1
公开(公告)日：2002-05-28
申请号：US09473032
申请日：1999-12-28
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21302
CPC分类号： C25D5/34 , C25D7/123
摘要： A method is disclosed to improve copper process integration in the forming copper interconnects in integrated circuits. This is accomplished by integrating the process of forming a copper seed layer in an interconnect structure such as a trench or a groove, with the process of plasma cleaning of the structure prior to the electroplating of copper into the trench. NH3 plasma can be used for this purpose. Or, H2/N2 thermal reduction can also be employed. The integrated process promotes well-controlled electro-chemical deposition (ECD) of copper for solid filling of the trench.
摘要翻译：公开了一种改进集成电路中形成铜互连的铜工艺集成的方法。这通过将铜晶种层形成在诸如沟槽或沟槽的互连结构中的过程与在电镀铜到沟槽之前对结构进行等离子体清洁的过程来实现。 NH3等离子体可用于此目的。或者也可以使用H 2 / N 2热还原。整合过程促进铜的良好控制的电化学沉积（ECD），用于固体填充沟槽。

114. 发明授权

US06287966B1 Low sheet resistance of titanium salicide process 失效
标题翻译：钛硅化物工艺的低表面电阻
公开(公告)号：US06287966B1
公开(公告)日：2001-09-11
申请号：US09303835
申请日：1999-05-03
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/28052 , H01L21/28273 , H01L21/28518 , H01L29/665
摘要： A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.
摘要翻译：一种通过额外的真空烘烤教导C-54 TiSix工艺的用于制备用于Titanium Salicide工艺的低薄层电阻的方法。本发明教导了在Si离子混合过程中在金属前HF浸渍之前的另外的真空烘烤步骤，PAI过程之前的PAI之前的另外的真空烘烤步骤，在金属前HF浸渍之前的另外的真空烘烤步骤 PAI过程。

115. 发明授权

US06225223B1 Method to eliminate dishing of copper interconnects 有权
标题翻译：消除铜互连凹陷的方法
公开(公告)号：US06225223B1
公开(公告)日：2001-05-01
申请号：US09374297
申请日：1999-08-16
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L21/7684
摘要： A method of forming an interconnect, comprising the following steps. A dielectric layer, having an upper surface, is formed over a semiconductor structure. A trench, having side walls and a bottom, is formed within the dielectric layer. A barrier layer is then formed over the dielectric layer and lining the trench's side walls and bottom. A first copper layer is deposited on the barrier layer, filling the lined trench and blanket filling the barrier layer covered dielectric layer. The first copper layer is planarized, exposing the upper surface of the dielectric layer and forming a dished copper filled trench. A second copper layer is selectively deposited on the dished copper filled trench by either electroless plating or chemical vapor deposition (CVD). The second copper layer extending above the upper surface of the dielectric layer. The second copper layer is then planarized to form an essentially planar copper filled trench, or interconnect, level with the upper surface of said dielectric layer.
摘要翻译：一种形成互连的方法，包括以下步骤。具有上表面的介电层形成在半导体结构之上。具有侧壁和底部的沟槽形成在电介质层内。然后在电介质层上形成阻挡层，并衬在沟槽的侧壁和底部。第一铜层沉积在阻挡层上，填充衬里的沟槽并覆盖填充阻挡层覆盖的电介质层。第一铜层被平坦化，暴露电介质层的上表面并形成填充有铜的沟槽。通过无电镀或化学气相沉积（CVD），第二铜层选择性地沉积在带有填充铜的填充沟槽上。第二铜层延伸到电介质层的上表面之上。然后将第二铜层平坦化以形成与所述电介质层的上表面基本上平面的铜填充沟槽或互连级。

116. 发明授权

US06181013B2 Method for selective growth of Cu3Ge or Cu5Si for passivation of damascene copper structures and device manufactured thereby 有权
标题翻译：选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件
公开(公告)号：US06181013B2
公开(公告)日：2001-01-30
申请号：US09524521
申请日：2000-03-13
申请人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
发明人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L2348
CPC分类号： H01L21/76867 , H01L21/7684 , H01L21/76849
摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.
摘要翻译：在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。在包括导电基板的暴露表面和电介质层的暴露的侧壁的电介质层上形成阻挡层。在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。从铜化合物的表面和阻挡层的表面蚀刻掉材料以通过蚀刻到电介质顶部水平来平坦化铜化合物，留下覆盖较窄孔中的铜导体的铜钝化化合物的薄层。

117. 发明授权

US6143657A Method of increasing the stability of a copper to copper interconnection process and structure manufactured thereby 有权
标题翻译：提高铜与铜互连工艺的稳定性的方法和由此制造的结构
公开(公告)号：US6143657A
公开(公告)日：2000-11-07
申请号：US225063
申请日：1999-01-04
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44 , H01L29/43
CPC分类号： H01L21/76867 , H01L21/76805 , H01L21/76843 , H01L21/76879 , H01L23/5226 , H01L23/532 , H01L23/53238 , H01L2924/0002 , Y10S257/915
摘要： A via is formed between a copper conductor and a second copper conductor in a thin film electronic device with a copper plug interconnecting the copper conductor and the second copper conductor. Form a stop layer over the first copper conductor and a dielectric layer over the stop layer. Pattern the dielectric and etch stop layers by etching a hole therethrough down into a copper conductor leaving an exposed surface of the copper conductor and exposed sidewalls of the dielectric layer and the etch stop layer. Grow a copper germanide (Cu.sub.3 Ge) compound, thin film at the base of the hole on the exposed surface of the copper conductor from exposure to germane GeH.sub.4 gas. Form a barrier layer over the copper germanide (Cu.sub.3 Ge) compound, thin film, the dielectric layer and the first copper conductor. The barrier layer forms a via hole in the hole. Form a second copper conductor including the copper plug over the barrier layer, the copper plug filling the narrow via hole.
摘要翻译：在具有将铜导体和第二铜导体互连的铜插头的薄膜电子器件中的铜导体和第二铜导体之间形成通孔。在第一铜导体上形成停止层，在停止层上形成介电层。通过将孔向下蚀刻到铜导体中来形成电介质和蚀刻停止层，留下铜导体的暴露表面和介电层和蚀刻停止层的暴露的侧壁。在铜导体的暴露表面上的孔的底部生长出锗化锗（Cu3Ge）复合物，暴露于锗锗GeH4气体中的薄膜。在铜锗化合物（Cu3Ge）化合物，薄膜，电介质层和第一铜导体上形成阻挡层。阻挡层在孔中形成通孔。在阻挡层上形成包括铜塞的第二铜导体，铜塞填充窄通孔。

118. 发明授权

US6130162A Method of preparing passivated copper line and device manufactured thereby 有权
标题翻译：钝化铜线的制作方法及其制造装置
公开(公告)号：US6130162A
公开(公告)日：2000-10-10
申请号：US224983
申请日：1999-01-04
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/443
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76849 , H01L21/76852 , H01L21/76885 , H01L2924/0002 , Y10S257/915
摘要： A method of forming a copper conductor for a thin film electronic device comprises: forming layers over a conductor into a stack of barrier layer superjacent on top of the substrate, a copper layer on top of the barrier layer, and a hard mask layer on top of the copper layer. The forming a mask on top of the hard mask layer and pattern the stack by etching through the layers down to the substrate on the sides of the mask forming the copper layer into a copper conductor line and leaving sidewalls of the copper conductor line exposed. Grow a copper germanide (Cu.sub.3 Ge) compound passivation layer is selectively grown only on the sidewalls of the copper conductor line.
摘要翻译：一种形成用于薄膜电子器件的铜导体的方法包括：在导体上形成层叠在衬底顶部以上的阻挡层堆叠，在阻挡层顶部的铜层和顶部的硬掩模层的铜层。在硬掩模层的顶部上形成掩模，并通过将层压蚀成形成铜层的掩模的侧面上的衬底到铜导体线中并且使铜导体线的侧壁露出而形成叠层。生长铜锗化合物（Cu3Ge）化合物钝化层仅选择性地生长在铜导线的侧壁上。

119. 发明授权

US06046108A Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby 有权
标题翻译：选择性生长Cu3Ge或Cu5Si用于钝化镶嵌铜结构的方法及其制造的器件
公开(公告)号：US06046108A
公开(公告)日：2000-04-04
申请号：US344402
申请日：1999-06-25
申请人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
发明人： Chung-Shi Liu , Chen-Hua Yu , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76867 , H01L21/7684 , H01L21/76849
摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planiarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.
摘要翻译：在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。在包括导电基底的暴露表面和电介质层暴露的侧壁的电介质层上形成阻挡层。在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。从铜化合物的表面和阻挡层的表面蚀刻掉材料，以通过蚀刻到电介质顶层来平面化铜化合物，留下在较窄的孔中覆盖铜导体的铜钝化化合物的薄层。

120. 发明授权

US09021682B2 Apparatus for stud bump formation 有权
标题翻译：用于柱形凸块形成的装置
公开(公告)号：US09021682B2
公开(公告)日：2015-05-05
申请号：US13527459
申请日：2012-06-19
申请人： Chien Ling Hwang , Yeong-Jyh Lin , Yi-Li Hsiao , Ming-Da Cheng , Tsai-Tsung Tsai , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
发明人： Chien Ling Hwang , Yeong-Jyh Lin , Yi-Li Hsiao , Ming-Da Cheng , Tsai-Tsung Tsai , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu
IPC分类号： H01R43/052 , H01L21/48 , H01L23/00
CPC分类号： H01L24/11 , H01L21/4853 , H01L24/13 , H01L24/78 , H01L2224/056 , H01L2224/1111 , H01L2224/1134 , H01L2224/13005 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13164 , H01L2224/13169 , H01L2224/451 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48 , H01L2224/7855 , H01L2224/78621 , H01L2224/85051 , H01L2224/854 , H01L2924/00011 , H01L2924/00012 , H01L2924/00014 , H01L2924/206 , Y10T29/49192 , Y10T29/49213 , Y10T29/514 , Y10T29/5177 , Y10T29/53217 , Y10T29/53235 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/01049 , H01L2224/4554
摘要： An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump.
摘要翻译：一种装置包括：线圈，其被配置为供应线，被配置为在所述线中形成切口的切割装置，以及被配置为结合所述线并形成柱形凸块的毛细管。该设备还被配置为拉动线在凹口处断裂，尾部区域附接到柱形凸块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式