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    • 112. 发明申请
    • Wireless transceiving apparatus for variability of signal processing band
    • 用于信号处理频带变化的无线收发装置
    • US20060135086A1
    • 2006-06-22
    • US11224811
    • 2005-09-12
    • Seon-Ho HanMun-Yang ParkHyun-Kyu YuCheon-Soo Kim
    • Seon-Ho HanMun-Yang ParkHyun-Kyu YuCheon-Soo Kim
    • H04B1/46
    • H04B1/405
    • Provided is a wireless transceiving apparatus for variability of signal processing band, in which at least one resonator of an analog processor and a VCO are simultaneously controlled using a frequency synthesizer, and a frequency of the VCO and a resonance frequency of the analog processor are controlled to have a rational number ratio, thereby capable of varying the signal processing band. The wireless transceiving apparatus includes: an analog processor having a plurality of resonators on a path of transmission/reception signals, for performing analog signal processing; a digital processor for performing digital signal processing on an output signal of the analog processor or data to be transmitted to the analog processor; and a frequency synthesizer for providing a local oscillation (LO) frequency and a controlling signal to the resonators of the analog processor so as to vary a signal processing band of the analog processor.
    • 提供了一种用于信号处理频带的可变性的无线收发装置,其中使用频率合成器同时控制模拟处理器和VCO的至少一个谐振器,并且控制VCO的频率和模拟处理器的谐振频率 具有有理数比,从而能够改变信号处理频带。 无线收发装置包括:模拟处理器,在发送/接收信号的路径上具有多个谐振器,用于执行模拟信号处理; 用于对模拟处理器的输出信号执行数字信号处理的数字处理器或将被发送到模拟处理器的数据; 以及用于向模拟处理器的谐振器提供本地振荡(LO)频率和控制信号以便改变模拟处理器的信号处理频带的频率合成器。
    • 118. 发明授权
    • Method of manufacturing a semiconductor device having buried elements
with electrical characteristic
    • 具有具有电特性的埋设元件的半导体器件的制造方法
    • US5286670A
    • 1994-02-15
    • US880892
    • 1992-05-08
    • Sang-Won KangHyun-Kyu YuWon-Gu Kang
    • Sang-Won KangHyun-Kyu YuWon-Gu Kang
    • H01L21/304H01L21/02H01L21/74H01L21/762H01L21/822H01L21/8242H01L23/52H01L23/535H01L27/04H01L27/10H01L27/108H01L27/12H01L21/302
    • H01L28/20H01L21/743H01L21/76248H01L21/76251H01L23/535H01L28/40H01L2924/0002Y10S148/012Y10S148/135
    • There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon layer thus doped to form a mirror surface; (e) depositing an insulating layer for connection on the handling wafer, and performing a thermal process to bond the handling wafer and the mirror surface through the insulating layer for connection; and (f) polishing the seed wafer until the first isolating insulator layer as a polishing stopper is exposed, to form the SOI substrate having an active region where a device is formed, by the invention the efficiency of chip area can be promoted.
    • 公开了一种具有掩埋SOI衬底的电气元件的半导体器件及其制造方法,本发明的制造方法包括以下步骤:(a)通过使用隔离掩模在晶种晶片上形成第一隔离绝缘体层, 覆盖所述第一隔离绝缘体层和所述晶种晶片的第二隔离绝缘体层,以及通过使用接触掩模在所述晶种晶片上形成接触来限定接触孔; (b)在所述第二隔离绝缘体层上沉积第一多晶硅层和所述接触并将杂质掺杂到所述第一多晶硅层中; (c)图案化所述第一多晶硅层以限定电元件,在所述电气元件周围沉积绝缘层,以及形成覆盖所述第二隔离绝缘体层和所述绝缘层的第二多晶硅层; (d)将杂质掺杂到所述第二多晶硅层中以与处理晶片连接,以及抛光所述掺杂的第二多晶硅层以形成镜面; (e)在所述处理晶片上沉积用于连接的绝缘层,以及执行热处理以通过所述绝缘层将所述处理晶片和所述镜表面接合以进行连接; 并且(f)研磨种子晶片直到作为抛光停止体的第一隔离绝缘体层露出为止,形成具有器件形成的有源区的SOI衬底,通过本发明可以提高芯片面积的效率。