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111. 发明申请

US20050006696A1 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US20050006696A1
公开(公告)日：2005-01-13
申请号：US10850408
申请日：2004-05-21
申请人： Mitsuhiro Noguchi , Akira Goda , Masayuki Tanaka
发明人： Mitsuhiro Noguchi , Akira Goda , Masayuki Tanaka
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L27/148 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0483 , H01L27/115 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/792
摘要： A semiconductor memory having an electrically writable/erasable memory cell includes a first gate insulating layer made from a compound containing silicon and oxygen; a first charge-storage layer being in contact with the first gate insulating layer made from a silicon nitride film, a silicon oxynitride film, or an alumina film; a second insulating layer thicker than the first gate insulting layer; a second charge-storage layer being in contact with the second insulating layer; a third insulating layer thicker than the first gate insulating layer being in contact with the second charge-storage layer; and a control electrode upon the third insulating layer.
摘要翻译：具有电可写/可擦除存储单元的半导体存储器包括由含硅和氧的化合物制成的第一栅极绝缘层; 与由氮化硅膜，氮氧化硅膜或氧化铝膜构成的第一栅极绝缘层接触的第一电荷存储层; 比第一栅极绝缘层厚的第二绝缘层; 与第二绝缘层接触的第二电荷存储层; 比所述第一栅极绝缘层更厚的与所述第二电荷存储层接触的第三绝缘层; 以及在所述第三绝缘层上的控制电极。

112. 发明授权

US10217515B2 Programming memory devices 有权
公开(公告)号：US10217515B2
公开(公告)日：2019-02-26
申请号：US15477048
申请日：2017-04-01
申请人： Akira Goda , Tommaso Vali , Carmine Miccoli , Pranav Kalavade
发明人： Akira Goda , Tommaso Vali , Carmine Miccoli , Pranav Kalavade
IPC分类号： G11C16/04 , G11C16/34 , G11C16/12 , G11C8/08
摘要： Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.

113. 发明授权

US09136128B2 Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials 有权
标题翻译：包括具有气隙的记忆体和其它低介电常数材料的方法和装置
公开(公告)号：US09136128B2
公开(公告)日：2015-09-15
申请号：US13222367
申请日：2011-08-31
申请人： Minsoo Lee , Akira Goda
发明人： Minsoo Lee , Akira Goda
IPC分类号： H01L29/788 , H01L21/28 , H01L29/66 , H01L21/764 , H01L29/423
CPC分类号： H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/7889
摘要： Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.
摘要翻译：各种实施例包括其形成装置和方法。一种这样的设备可以包括第一介电材料和第二介电材料，以及在第一介电材料和第二介电材料之间的导电材料。诸如浮动栅极或电荷阱的电荷存储元件位于第一介电材料和第二电介质材料之间并且与导电材料相邻。电荷存储元件具有第一表面和第二表面。第一和第二表面分别通过第一气隙和第二气隙与第一介电材料和第二电介质材料分开。公开了附加的装置和方法。

114. 发明授权

US08767487B2 Drain select gate voltage management 有权
标题翻译：漏极选择栅极电压管理
公开(公告)号：US08767487B2
公开(公告)日：2014-07-01
申请号：US12715530
申请日：2010-03-02
申请人： Akira Goda , Pranav Kalavade , Doyle Rivers
发明人： Akira Goda , Pranav Kalavade , Doyle Rivers
IPC分类号： G11C7/00
CPC分类号： G11C16/12 , G11C16/04 , G11C16/0433
摘要： Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.
摘要翻译：一些实施例包括在与编程多个存储器单元相关联的编程时间周期的第一部分期间操作以施加漏极选择栅极电压的第一值的装置，系统和方法，以及施加漏极选择的第二值在第二编程时间段的后续部分中，栅极电压与第一值不同。漏极选择栅极电压可以在单个编程周期中的编程脉冲组之间改变。第一和第二部分可以根据应用的编程脉冲的数量，已经完全编程的存储器单元的数量和/或其他条件来确定。公开了附加装置，系统和方法。

115. 发明申请

US20140169093A1 ERASE AND SOFT PROGRAM FOR VERTICAL NAND FLASH 有权
标题翻译：用于垂直NAND闪存的擦除和软件程序
公开(公告)号：US20140169093A1
公开(公告)日：2014-06-19
申请号：US13719558
申请日：2012-12-19
申请人： Krishna K. Parat , Pranav Kalavade , Koichi Kawai , Akira Goda
发明人： Krishna K. Parat , Pranav Kalavade , Koichi Kawai , Akira Goda
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C8/12 , G11C16/04 , G11C16/3409 , G11C16/3445
摘要： Methods, and apparatuses to erase and or soft program a block of NAND memory may include performing an erase cycle on a block of NAND memory comprising two or more sub-blocks, verifying the two or more sub-blocks until a sub-block fails to verify, stopping the verification in response to the failed verify, performing another erase cycle on the block of NAND memory, and re-starting to verify the two or more sub-blocks at the sub-block that failed to verify
摘要翻译：擦除和/或软件编程NAND存储器块的方法和装置可以包括在包括两个或多个子块的NAND存储器块上执行擦除周期，验证两个或更多个子块直到子块失败验证，停止验证以响应失败的验证，在NAND存储器块上执行另一个擦除周期，并重新启动以验证子块处的两个或更多个子块，验证失败

116. 发明授权

US08693231B2 Couplings within memory devices 有权
标题翻译：存储器件内的联轴器
公开(公告)号：US08693231B2
公开(公告)日：2014-04-08
申请号：US13495287
申请日：2012-06-13
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C5/06
CPC分类号： G11C7/02 , G11C7/1036 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.
摘要翻译：存储器件包括耦合到第一多路复用器门的第一源极/漏极区域的第一位线，耦合到第二多路复用器栅极的第一源极/漏极区域的第二位线以及耦合到第二多路复用器栅极的输入的感测器件第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第二源极/漏极区域。感测装置的输入形成在与形成第一和第二位线中的至少一个的垂直电平不同的垂直电平处。

117. 发明申请

US20140063960A1 MEMORY PROGRAM DISTURB REDUCTION 有权
标题翻译：存储器程序减少干扰
公开(公告)号：US20140063960A1
公开(公告)日：2014-03-06
申请号：US13600623
申请日：2012-08-31
申请人： Akira Goda , Mark Helm , Pranav Kalavade , Charan Srinivasan
发明人： Akira Goda , Mark Helm , Pranav Kalavade , Charan Srinivasan
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.
摘要翻译：一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。一种这样的方法可以包括在编程的第一次通过期间将第一偏置电压值应用于源极选择栅极以将存储器单元与源极隔离，在第一次处理期间将编程电压施加到存储器单元的页面的访问线编程的通过，以及在源选择栅极施加第二偏置电压值以在第二次编程期间隔离存储器单元与源极。公开了其它装置，系统和方法。

118. 发明授权

US08619474B2 Data line management in a memory device 有权
标题翻译：存储设备中的数据线管理
公开(公告)号：US08619474B2
公开(公告)日：2013-12-31
申请号：US12556941
申请日：2009-09-10
申请人： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
发明人： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
IPC分类号： G11C7/02
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C2211/5621
摘要： Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.
摘要翻译：公开了存储器件和方法，例如被配置为在程序操作的第一部分期间向数据线施加第一程序禁止偏置的器件，并且在程序操作的第二部分期间对数据线施加第二程序禁止偏置。第二个程序禁止偏置大于第一个程序抑制偏置。

119. 发明申请

US20130277731A1 APPARATUSES AND METHODS OF FORMING APPARATUSES USING A PARTIAL DECK-BY-DECK PROCESS FLOW 审中-公开
标题翻译：使用部分DECK-BY-DECK工艺流程形成装置的装置和方法
公开(公告)号：US20130277731A1
公开(公告)日：2013-10-24
申请号：US13450299
申请日：2012-04-18
申请人： Akira Goda , Roger W. Lindsay
发明人： Akira Goda , Roger W. Lindsay
IPC分类号： H01L27/088 , H01L21/8239 , H01L27/08 , H01L21/822
CPC分类号： G11C16/0408 , H01L27/11556 , H01L27/11582
摘要： Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.
摘要翻译：各种实施例包括诸如形成在两个或更多个堆叠甲板上的存储单元的方法和装置。一种方法包括在衬底上形成具有第一级导体材料和第一级电介质材料的第一层板。导体材料的每个级别通过第一级介电材料中的至少一个与相邻级别的导体材料分开。通过导体材料和电介质材料的第一层形成第一开口。形成至少部分地填充第一开口的牺牲材料。在第一层甲板上形成第二层甲板。第二层具有第二层导体材料和第二层介质材料，其中导电材料的每一层通过至少一个第二层介质材料与相邻层的导体材料分开。公开了附加的装置和方法。

120. 发明授权

US08514629B2 Method for memory cell erasure with a programming monitor of reference cells 有权
标题翻译：用参考单元的编程监视器进行存储单元擦除的方法
公开(公告)号：US08514629B2
公开(公告)日：2013-08-20
申请号：US13602762
申请日：2012-09-04
申请人： Akira Goda , Andrei Mihnea
发明人： Akira Goda , Andrei Mihnea
IPC分类号： G11C16/16
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
摘要翻译：本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

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