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101. 发明申请

US20150019840A1 Highly Integrated Scalable, Flexible DSP Megamodule Architecture 有权
标题翻译：高度集成的可扩展，灵活的DSP Megamodule架构
公开(公告)号：US20150019840A1
公开(公告)日：2015-01-15
申请号：US14331986
申请日：2014-07-15
申请人： Texas Instruments Incorporated
发明人： Timothy D. Anderson , Joseph Zbiciak , Duc Quang Bui , Abnijeet A. Chachad , Kai Chirca , Naveen Bhoria , Matthew D. Pierson , Daniel Wu
IPC分类号： G06F9/30 , G06F9/345
CPC分类号： G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3822 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F2212/452 , G06F2212/60
摘要： This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.
摘要翻译：本发明解决了将一系列有趣的技术实现到单个块中。每个DSP CPU都有一个流式引擎。流式引擎包括：可以从L2请求512位/周期的SE到L2接口; SE和L2接口之间的松散绑定，允许单个流以1024位/周期达到峰值; 单向一致性，其中SE看到所有较早的写入缓存在系统中，而不是在流打开之后发生的写入; 通过单位奇偶校验，通过奇偶校验错误半自动重新启动，完全保护其内部存储器内的单位数据错误。

102. 发明授权

US08935504B1 Execution of a perform frame management function instruction 有权
标题翻译：执行执行帧管理功能指令
公开(公告)号：US08935504B1
公开(公告)日：2015-01-13
申请号：US14136086
申请日：2013-12-20
申请人： International Business Machines Corporation
发明人： Charles W. Gainey, Jr. , Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Gustav E. Sittmann, III
IPC分类号： G06F13/00 , G06F12/08
CPC分类号： G06F9/30043 , G06F3/0604 , G06F3/0605 , G06F3/0644 , G06F3/0652 , G06F3/0664 , G06F3/0673 , G06F9/30003 , G06F9/30098 , G06F9/30101 , G06F9/30145 , G06F9/45537 , G06F9/45545 , G06F9/45558 , G06F12/023 , G06F12/08 , G06F12/0891 , G06F12/1009 , G06F2009/45583 , G06F2212/1041 , G06F2212/151 , G06F2212/656 , G06F2212/657 , G06F2212/69
摘要： Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.
摘要翻译：为框架管理操作提供优化，包括可分页访客请求的清晰操作和/或设置的存储密钥操作。在没有驻留在主机内存中的帧上，执行操作，而不需要主机干预。操作可以在可分页客人发出的指令中指定。

103. 发明授权

US08914619B2 High-word facility for extending the number of general purpose registers available to instructions 有权
标题翻译：用于扩展可用于指令的通用寄存器数量的高位设备
公开(公告)号：US08914619B2
公开(公告)日：2014-12-16
申请号：US12820735
申请日：2010-06-22
申请人： Dan F. Greiner , Marcel Mitran , Timothy J. Slegel
发明人： Dan F. Greiner , Marcel Mitran , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30105 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/322 , G06F9/342
摘要： A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed.
摘要翻译：计算机采用一组通用寄存器（GPR）。每个GPR包括多个部分。诸如操作系统和以大GPR模式运行的应用程序等程序可访问完整的GPR，但是以小GPR模式运行的应用程序等程序只能一次访问一部分。指令操作码，在小GPR模式下，可以确定访问哪个部分。

104. 发明授权

US08892848B2 Processor and system using a mask register to track progress of gathering and prefetching elements from memory 有权
标题翻译：处理器和系统使用掩码寄存器跟踪从内存中采集和预取元素的进度
公开(公告)号：US08892848B2
公开(公告)日：2014-11-18
申请号：US13175953
申请日：2011-07-05
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G06F9/312 , G06F9/30 , G06F12/02 , G06F9/345 , G06F9/38 , G06F15/80
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译：一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。描述和要求保护其他实施例。

105. 发明申请

US20140333635A1 HIERARCHICAL HASH TABLES FOR SIMT PROCESSING AND A METHOD OF ESTABLISHING HIERARCHICAL HASH TABLES 有权
标题翻译：用于SIMT处理的分层扫描表和建立分层哈希表的方法
公开(公告)号：US20140333635A1
公开(公告)日：2014-11-13
申请号：US13891614
申请日：2013-05-10
申请人： NVIDIA CORPORATION
发明人： Julien Demouth
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/30098 , G06F9/3836 , G06F9/3885 , G06F17/3033
摘要： A graphical processing unit having an implementation of a hierarchical hash table thereon, a method of establishing a hierarchical hash table in a graphics processing unit and GPU computing system are disclosed herein. In one embodiment, the graphics processing unit includes: (1) a plurality of parallel processors, wherein each of the plurality of parallel processors includes parallel processing cores, a shared memory coupled to each of the parallel processing cores, and registers, wherein each one of the registers is uniquely associated with one of the parallel processing cores and (2) a controller configured to employ at least one of the registers to establish a hierarchical hash table for a key-value pair of a thread processing on one of the parallel processing cores.
摘要翻译：具有其上分层哈希表的实现的图形处理单元，在图形处理单元和GPU计算系统中建立分层哈希表的方法。在一个实施例中，图形处理单元包括：（1）多个并行处理器，其中多个并行处理器中的每一个并行处理器包括并行处理核，耦合到每个并行处理核和共享存储器的共享存储器，其中每个所述寄存器与所述并行处理核心之一唯一相关联，以及（2）控制器，被配置为使用所述寄存器中的至少一个来为所述并行处理之一上的线程处理的键值对建立分层哈希表核心。

106. 发明申请

US20140281414A1 REORDER-BUFFER-BASED DYNAMIC CHECKPOINTING FOR RENAME TABLE REBUILDING 有权
标题翻译：基于重构缓冲区的动态检测用于重命名表重建
公开(公告)号：US20140281414A1
公开(公告)日：2014-09-18
申请号：US13831488
申请日：2013-03-14
申请人： Ravi Iyengar , Prarthna Santhanakrishnan
发明人： Ravi Iyengar , Prarthna Santhanakrishnan
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/384 , G06F9/3855 , G06F9/3863
摘要： Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a dynamic mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB.
摘要翻译：无序的CPU，设备和方法减少了管道停止的时间，从而重建重命名表，例如由于错误预测。微处理器可以包括具有解码器，调度器和至少一个执行单元的管道。重命名表存储重命名数据，并且检查点表（“CPT”）存储从分派器接收的重命名数据。重新排序缓冲区（“ROB”）存储ROB数据，并且与CPT具有动态映射关系。如果重命名表被刷新，例如由于错误预测，则重命名表至少部分地通过并行复制存储在CPT中的重命名数据，与步行ROB协调来重建。

107. 发明申请

US20140281405A1 OPTIMIZING PERFORMANCE FOR CONTEXT-DEPENDENT INSTRUCTIONS 有权
标题翻译：优化性能的背景相关指示
公开(公告)号：US20140281405A1
公开(公告)日：2014-09-18
申请号：US13841576
申请日：2013-03-15
申请人： QUALCOMM Incorporated
发明人： Daren Eugene Streett , Brian Michael Stempel , Thomas Philip Speier , Rodney Wayne Smith , Michael Scott McIlvaine , Kenneth Alan Dockser , James Norris Dieffenderfer
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30189 , G06F9/3842 , G06F9/3863
摘要： A processor includes a queue for storing instructions processed within the context of a current value of a register field, where for some embodiments the instruction is undefined or defined, depending upon the register field at time of processing. After a write instruction (an instruction that writes to the register field) executes, the queue is searched for any entries that contain instructions that depend upon the executed write instruction. Each such entry stores the value of the register field at the time the instruction in the entry was processed. If such an entry is found in the queue and its stored value of the register field does not match the value that the write instruction wrote to the register field, then the processor flushes the pipeline and restarts at a state so as to correctly execute the instruction.
摘要翻译：处理器包括用于存储在寄存器字段的当前值的上下文中处理的指令的队列，其中对于一些实施例，取决于处理时的寄存器字段，指令是未定义的或定义的。在执行写入指令（写入寄存器字段的指令）之后，将搜索包含依赖于执行的写入指令的指令的任何条目。每个这样的条目存储处理条目中的指令时的寄存器字段的值。如果在队列中找到这样的条目，并且其寄存器字段的存储值与写入指令写入寄存器字段的值不匹配，则处理器刷新流水线并在一个状态下重新启动，以便正确地执行指令。

108. 发明申请

US20140281400A1 Systems, Apparatuses,and Methods for Zeroing of Bits in a Data Element 有权
标题翻译：数据元素中位的归零的系统，设备和方法
公开(公告)号：US20140281400A1
公开(公告)日：2014-09-18
申请号：US13840669
申请日：2013-03-15
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30036 , G06F9/30098 , G06F9/30149
摘要： Embodiments of systems, methods and apparatuses for execution a NAME instruction are described. The execution of a VPBZHI causes, on a per data element basis of a second source, a zeroing of bits higher (more significant) than a starting point in the data element. The starting point is defined by the contents of a data element in a first source. The resultant data elements are stored in a corresponding data element position of a destination.
摘要翻译：描述用于执行NAME指令的系统，方法和装置的实施例。 VPBZHI的执行在基于每个数据元素的第二源上导致比数据元素中的起始点更高（更高有效）的位的归零。起始点由第一个数据元素的内容定义。所得数据元素存储在目的地的相应数据元素位置。

109. 发明申请

US20140258687A1 MICRO-OPS INCLUDING PACKED SOURCE AND DESTINATION FIELDS 有权
标题翻译：包括包装来源和目的地的微型OPS
公开(公告)号：US20140258687A1
公开(公告)日：2014-09-11
申请号：US13790661
申请日：2013-03-08
申请人： Teik-Chung TAN , Bradley Gene BURGESS , Ravi IYENGAR
发明人： Teik-Chung TAN , Bradley Gene BURGESS , Ravi IYENGAR
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/30036 , G06F9/30105 , G06F9/384
摘要： A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming.
摘要翻译：提供了一种用于在微处理器中重新注册之前的寄存器封装的方法和装置。该方法包括：接收从一个或多个指令解码的多个微操作（微操作）; 将包含在微操作系统中的多个寄存器根据重新启动器的预设数量的重命名端口包含多个打包寄存器，其中打印寄存器结构被读取或写入用于寄存器重命名; 并发送用于注册重命名的打包寄存器。

110. 发明申请

US20140244978A1 CHECKPOINTING REGISTERS FOR TRANSACTIONAL MEMORY 有权
标题翻译：检查交易记录寄存器
公开(公告)号：US20140244978A1
公开(公告)日：2014-08-28
申请号：US13781403
申请日：2013-02-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： John M. King
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/30098 , G06F9/3857 , G06F9/3863
摘要： The present invention provides a method and apparatus for checkpointing registers for transactional memory. Some embodiments of the apparatus include first rename logic configured to map up to a predetermined number of architectural registers to corresponding first physical registers that hold first values associated with the architectural registers. The mapping is responsive to a transaction modifying one or more of the first values associated with the architectural registers. Some embodiments of the apparatus also include microcode configured to write contents of the first physical registers to a memory in response to the transaction modifying first values associated with a number of the architectural registers that is larger than the predetermined number.
摘要翻译：本发明提供了一种用于检查事件存储器的寄存器的方法和装置。该装置的一些实施例包括第一重命名逻辑，其被配置为将高达预定数量的架构寄存器映射到相应的第一物理寄存器，该第一物理寄存器保存与架构寄存器相关联的第一值。映射响应于修改与架构寄存器相关联的一个或多个第一值的事务。该装置的一些实施例还包括被配置为响应于事务修改将第一物理寄存器的内容写入存储器的微代码，修改与多于该预定数量的多个架构寄存器相关联的第一值。

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