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101. 发明授权

US07683663B1 Authorization of an implementation of a user design in a programmable integrated circuit 有权
标题翻译：授权在可编程集成电路中实现用户设计
公开(公告)号：US07683663B1
公开(公告)日：2010-03-23
申请号：US12353234
申请日：2009-01-13
申请人： Chih-Ming Tsai
发明人： Chih-Ming Tsai
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G06F21/10 , G06F21/76 , H03K19/17768
摘要： A system implements and authorizes use of a user design. A non-volatile memory stores combined configuration data including first configuration data for implementing a user design and an authorization module, and second configuration data for implementing a generator of a check code. In response to a reset, a programmable integrated circuit loads the first configuration data to implement the user design and the authorization module. The implemented authorization module generates an activation code from an identifier when the check code is available from the non-volatile memory and enables the user design when the check and activation codes match. The programmable integrated circuit loads the second configuration data to implement the generator when the check code is not available from the non-volatile memory. The implemented generator erases the second configuration data from the non-volatile memory, generates the check code from the identifier, and stores the check code in the non-volatile memory.
摘要翻译：系统实现和授权使用用户设计。非易失性存储器存储包括用于实现用户设计的第一配置数据和授权模块的组合配置数据，以及用于实现校验码的生成器的第二配置数据。响应于复位，可编程集成电路加载第一配置数据以实现用户设计和授权模块。当检查码可从非易失性存储器获得时，所实现的授权模块从标识符产生激活码，并且当支票和激活码匹配时使用户设计。当非易失性存储器中的检查码不可用时，可编程集成电路加载第二配置数据以实现发生器。实施的发生器从非易失性存储器擦除第二配置数据，从标识符生成检查码，并将检查码存储在非易失性存储器中。

102. 发明申请

US20090198991A1 TRUSTED BOOT 有权
公开(公告)号：US20090198991A1
公开(公告)日：2009-08-06
申请号：US12366602
申请日：2009-02-05
申请人： John R. Owens , John C. Andolina , Stuart Shanken , Richard L. Quintana
发明人： John R. Owens , John C. Andolina , Stuart Shanken , Richard L. Quintana
IPC分类号： G06F9/445
CPC分类号： G06F21/575 , G06F21/76 , G06F2221/2143
摘要： In one embodiment, a method for trusted booting of a cryptographic processor system is disclosed. Default image(s) is loaded into a field-programmable logic chip or circuit (FPLC). The default image(s) cannot perform cryptographic processing, but can perform a first algorithm that is unclassified. A processor, internal or external to the FPLC, can be used with the default image. A multi-layer or multi-part key has portions stored in two different places. A protected image is decrypted with the multi-layer key using the first algorithm and loaded into the FPLC. Cryptographic processing is performed using a second algorithm classified by the government.
摘要翻译：在一个实施例中，公开了一种用于信令引导密码处理器系统的方法。默认图像被加载到现场可编程逻辑芯片或电路（FPLC）中。默认图像不能执行加密处理，但可以执行未分类的第一个算法。 FPLC内部或外部的处理器可以与默认图像一起使用。多层或多部分键具有存储在两个不同位置的部分。使用第一种算法利用多层密钥对被保护的图像进行解密并加载到FPLC中。使用由政府分类的第二种算法进行加密处理。

103. 发明申请

US20080258762A1 ASICs HAVING PROGRAMMABLE BYPASS OF DESIGN FAULTS 有权
标题翻译：具有设计故障可编程的ASIC的ASIC
公开(公告)号：US20080258762A1
公开(公告)日：2008-10-23
申请号：US12145275
申请日：2008-06-24
申请人： James T. KOO
发明人： James T. KOO
IPC分类号： H03K19/173
CPC分类号： G06F21/76 , G01R31/3177 , G06F11/0706 , G06F11/0751 , G06F11/079 , G06F11/0793 , G06F11/20
摘要： A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times when the fault-infected ASIC block is about to perform a fault-infected operation (bug-infected operation). The substitution or bypass does not have to be a permanent one that is in effect at all times for the entirety of the fault-infected ASIC block. Instead affected outputs of the faulty ASIC block can be disabled from working just at the time they would otherwise initiate or propagate an error. Such fault-infected operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed pro-Logic at the appropriate times. Thus, a fault-infected ASIC block that is 99% good (for example) and operates improperly just 1% of the time can continue to be gainfully used for that 99% of the time when its operations are fault free and can be blocked from having its erroneous output(s) used only in the 1% time periods (example) when its behavior is faulty. During those faulty times, a relatively small amount of the pro-Logic can be used as a fault-correcting or fault-bypassing substitute for the fault-infected ASIC block. This substitution or bypassing can be activated after initial design of the mostly-ASIC circuitry and/or after pilot production and/or mass production thereby providing for cost saving and faster time to market and/or for repair or maintenance even years after installation and use of the mostly-ASIC device.
摘要翻译：大多数ASIC设备中包含相对少量的可编程或可重新编程的逻辑（pro-Logic），以便这样的可重新编程逻辑可以用作替代或绕过故障感染的ASIC块（如果有的话）有时候，故障感染的ASIC块即将执行故障感染操作（错误感染的操作）。替代或旁路不一定是永久性的，在整个故障感染ASIC块的任何时候都是有效的。故障ASIC块的相反影响的输出可以在其他情况下启动或传播错误时被禁止工作。临时停用的ASIC块的这种故障感染操作可以在适当的时间被适当编程的pro-Logic代替。因此，99％的故障感染的ASIC块（例如）并且仅在1％的时间内不正确地运行，可以在其操作无故障的99％的时间内继续有效地使用，并且可以被阻止其错误输出仅在其行为有故障的1％时间段（例如）中使用。在这些故障时期，相对较少量的pro-Logic可以用作故障修复或故障旁路替代故障感染的ASIC块。这种替代或旁路可以在主要ASIC电路的初始设计之后和/或在试生产和/或批量生产之后被激活，从而提供成本节省和更快的上市时间和/或在安装和使用几年后的维修或维护的大多数ASIC设备。

104. 发明申请

US20070247182A1 Protection of security key information 审中-公开
标题翻译：保护安全关键信息
公开(公告)号：US20070247182A1
公开(公告)日：2007-10-25
申请号：US11395871
申请日：2006-03-31
申请人： Timothy Beatty , Mark Fullerton , Tom Mozdzen
发明人： Timothy Beatty , Mark Fullerton , Tom Mozdzen
IPC分类号： H03K19/00
CPC分类号： G06F21/76 , G06F21/71 , G11C17/16 , G11C17/18
摘要： A protection circuit is disclosed, for preventing access to stored security key data after the security key is no longer used. The protection circuit performs operations on a programming circuit used to program a bit of the security key. The protection circuit prevents inspection of the security key bit, using several techniques. Subsequent inspection of the programming circuit does not reveal the value of the security key bit.
摘要翻译：公开了一种用于在不再使用安全密钥之后防止对存储的安全密钥数据的访问的保护电路。保护电路对用于编程安全密钥位的编程电路进行操作。保护电路使用几种技术来防止对安全密钥位的检查。对编程电路的后续检查不会显示安全密钥位的值。

105. 发明申请

US20060059574A1 System for securely configuring a field programmable gate array or other programmable hardware 审中-公开
标题翻译：用于安全配置现场可编程门阵列或其他可编程硬件的系统
公开(公告)号：US20060059574A1
公开(公告)日：2006-03-16
申请号：US10938775
申请日：2004-09-10
申请人： Camil Fayad , John Li , Siegfried Sutter
发明人： Camil Fayad , John Li , Siegfried Sutter
IPC分类号： G06F11/00
CPC分类号： H03K19/17768 , G06F21/76
摘要： A system and method are provided for securely providing configuration information, that is, programming, to programmable hardware such as a Field Programmable Gate Array (FPGA) or a Programmable Logic Device (PLD). Security is provided by first verifying authority to enter configuration information via the decryption of an encrypted certificate of authority. The decryption is carried out using a cryptography engine disposed on the chip containing the programmable hardware. Additionally, the configuration information is itself provided in an encrypted form which requires recognition of the certificate of authority in order to decrypt it and to place it in storage locations within the programmable hardware. In this manner, the flexibility advantages of programmable hardware are fully met without the disadvantage of the programmable hardware being compromised by other users.
摘要翻译：提供了一种系统和方法，用于将诸如现场可编程门阵列（FPGA）或可编程逻辑器件（PLD）等可编程硬件的配置信息即编程安全地提供。安全性由第一验证机构通过解密加密的授权证书来输入配置信息。使用设置在包含可编程硬件的芯片上的密码引擎进行解密。此外，配置信息本身以加密形式提供，其需要识别权限证书以便将其解密并将其放置在可编程硬件内的存储位置中。以这种方式，可完全满足可编程硬件的灵活性优势，而没有可编程硬件被其他用户损害的缺点。

106. 发明申请

US20060059368A1 System and method for processing by distinct entities securely configurable circuit chips 审中-公开
标题翻译：通过不同实体处理的系统和方法安全可配置的电路芯片
公开(公告)号：US20060059368A1
公开(公告)日：2006-03-16
申请号：US10938834
申请日：2004-09-10
申请人： Camil Fayad , John Li , Siegfried Sutter
发明人： Camil Fayad , John Li , Siegfried Sutter
IPC分类号： H04L9/00 , G06F12/14 , H04L9/32 , G06F11/30
CPC分类号： G06F21/72 , G06F21/76 , G06F21/87 , G06F2221/2115 , G06F2221/2143 , H04L9/3247 , H04L9/3263 , H04L9/3297 , H04L2209/56
摘要： A system and method are provided in which a third party chip vendor is enabled to securely program an electronic circuit chip supplied from a chip manufacturer. The chip vendor supplies a vendor's public cryptography key to the chip manufacturer who hard codes it on the chip along with a chip private key and a chip public key. One or more cryptographic engines on the chip, which preferably has a tamper resistant/detecting boundary, are used to decrypt program instructions supplied to the chip after having been encrypted with the vendor's private key and the chip public key. The chip includes a processor and an associated memory which receives a version of the instructions decrypted with the chip private key and the vendor's public key. The chip also preferably includes programmable hardware which is also securely programmable by the downstream chip vendor. The chip, as processed by the chip vendor is shipped with a battery in place to provide power for maintaining data held in volatile memory portions of the chip.
摘要翻译：提供了一种系统和方法，其中第三方芯片供应商能够安全地编程从芯片制造商提供的电子电路芯片。芯片供应商向芯片制造商提供供应商的公共密码密钥，芯片制造商将其与芯片私钥和芯片公钥一起在芯片上进行硬编码。优选地具有防篡改/检测边界的芯片上的一个或多个密码引擎被用于在用供应商的私钥和芯片公开密钥加密之后解密提供给芯片的程序指令。芯片包括处理器和相关联的存储器，其接收用芯片私钥和供应商的公钥解密的指令的版本。该芯片还优选地包括也可由下游芯片供应商可编程的可编程硬件。由芯片供应商处理的芯片随机提供电池，以提供用于维持保持在芯片的易失性存储器部分中的数据的电力。

107. 发明申请

US20060020907A1 Copy protection method and system for programmable gate array 有权
公开(公告)号：US20060020907A1
公开(公告)日：2006-01-26
申请号：US11186967
申请日：2005-07-22
申请人： Masahiro Tonami , Kozaburo Nakamura , Atsushi Kondo , Shigeaki Funaki , Koji Yasuda
发明人： Masahiro Tonami , Kozaburo Nakamura , Atsushi Kondo , Shigeaki Funaki , Koji Yasuda
IPC分类号： G06F9/44
CPC分类号： G06F9/4401 , G06F21/76
摘要： The present invention relates to a programmable-gate-array copy protection method and a system which prevent unauthorized copying of an FPGA program. A copy protection method for a field-programmable gate array, the method comprising a step of causing a user-specific gate array to boot a user circuit data to the field-programmable gate array, the user-specific gate array being connected to the field-programmable gate array and a memory device in which the user circuit data is stored and being pre-programmed at a semiconductor-vender's factory.

108. 发明申请

US20030229799A1 Semiconductor integrated circuits, data transfer systems, and the method for data transfer 失效
标题翻译：半导体集成电路，数据传输系统和数据传输方法
公开(公告)号：US20030229799A1
公开(公告)日：2003-12-11
申请号：US10391562
申请日：2003-03-20
发明人： Yoshio Kaneko
IPC分类号： G06F012/14
CPC分类号： G06F21/75 , G06F21/76
摘要： A semiconductor integrated circuit configured for connection to an external ROM includes a decryption code block storing a decryption code; a decoder circuit connected to the decryption code block and decrypting encrypted data such that the encrypted data can be stored in the external ROM, by utilizing the decryption code; a configuration circuit connected to the decoder circuit; an FPGA circuit connected to the configuration circuit, the circuit structure of the FPGA circuit determined by the configuration circuit; and an internal circuit connected to the FPGA circuit, the circuit operation of which is determined by the FPGA circuit.
摘要翻译：配置用于连接到外部ROM的半导体集成电路包括存储解密码的解密码块; 连接到解密码块并解密加密数据的解码器电路，以便通过利用解密码将加密数据存储在外部ROM中; 连接到解码器电路的配置电路; 连接到配置电路的FPGA电路，FPGA电路的电路结构由配置电路决定; 以及连接到FPGA电路的内部电路，其电路工作由FPGA电路决定。

109. 发明授权

US06654889B1 Method and apparatus for protecting proprietary configuration data for programmable logic devices 有权
标题翻译：用于保护可编程逻辑器件专有配置数据的方法和装置
公开(公告)号：US06654889B1
公开(公告)日：2003-11-25
申请号：US09253401
申请日：1999-02-19
申请人： Stephen M. Trimberger
发明人： Stephen M. Trimberger
IPC分类号： H04L932
CPC分类号： H03K19/17768 , G06F21/76 , H04L9/0625 , H04L9/0643 , H04L9/3236 , H04L2209/12
摘要： Described are a method of programming a programmable logic device using encrypted configuration data and a programmable logic device (PLD) adapted to use such encrypted data. A PLD is adapted to include a decryptor having access to a non-volatile memory element programmed with a secret decryption key. Some or all of the decryptor can be instantiated in configurable logic on the FPGA. Encrypted configuration data representing some desired circuit functionality is presented to the decryptor. The decryptor then decrypts the configuration data, using the secret decryption key, and configures the FPGA with the decrypted configuration data. Some embodiments include authentication circuitry that performs a hash function on the configuration data used to instantiate the decryptor on the PLD. The result of the hash function is compared to a proprietary hash key programmed into the PLD. Only those configuration data that produce the desired hash result will instantiate decryptors that have access to the decryption key.
摘要翻译：描述了使用加密配置数据编程可编程逻辑器件的方法和适于使用这种加密数据的可编程逻辑器件（PLD）。 PLD适于包括具有对使用秘密解密密钥编程的非易失性存储器元件的访问的解密器。部分或全部解密器可以在FPGA上的可配置逻辑中实例化。将代表一些期望的电路功能的加密配置数据提供给解密器。解密器然后使用秘密解密密钥解密配置数据，并使用解密的配置数据配置FPGA。一些实施例包括对用于在PLD上实例化解密器的配置数据执行散列函数的认证电路。将哈希函数的结果与编程到PLD中的专有散列密钥进行比较。只有产生所需哈希结果的那些配置数据将实例化具有访问解密密钥的解密器。

110. 发明申请

US20030212897A1 Method and system for maintaining secure semiconductor device areas 审中-公开
标题翻译：用于维护半导体装置安全区域的方法和系统
公开(公告)号：US20030212897A1
公开(公告)日：2003-11-13
申请号：US09932408
申请日：2001-08-18
发明人： Russell Dickerson , Antonio Guillermo
IPC分类号： H04L009/00 , G06F009/455
CPC分类号： G06F21/79 , G06F21/71 , G06F21/72 , G06F21/74 , G06F21/76 , G06F2221/2105
摘要： A method and system for preventing access to secure areas of semiconductor devices using a control signal in conjunction with a secure area access obstruction circuit. A semiconductor device may have a user mode and a supervisor mode. When entering a supervisor mode, a control signal may transition from one logic state to another. Embodiments of the present invention utilize the control signal in conjunction with the secure area access obstruction circuit to prevent access to secure areas of the semiconductor device.
摘要翻译：一种用于使用控制信号与安全区域访问障碍电路一起防止访问半导体装置的安全区域的方法和系统。半导体器件可以具有用户模式和管理器模式。当进入管理员模式时，控制信号可以从一个逻辑状态转换到另一个逻辑状态。本发明的实施例结合安全区域访问障碍电路利用控制信号，以防止进入半导体器件的安全区域。

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