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101. 发明授权

US09654142B2 System and method for conveying information 有权
公开(公告)号：US09654142B2
公开(公告)日：2017-05-16
申请号：US14335735
申请日：2014-07-18
申请人： Silicon Graphics International Corp.
发明人： Steven C. Miller , Thomas Edward McGee , Bruce Alan Strangfeld
IPC分类号： G06F15/16 , H03M13/05 , G06F13/42 , G06F15/167 , H04J3/16 , G06F3/00 , G06F13/00
CPC分类号： H03M13/05 , G06F13/4217 , G06F15/16
摘要： A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.

102. 发明申请

US20170102734A1 APPARATUS AND METHOD FOR AUTOMATICALLY ALIGNING DATA SIGNALS AND STROBE SIGNALS ON A SOURCE SYNCRHONOUS BUS 审中-公开
公开(公告)号：US20170102734A1
公开(公告)日：2017-04-13
申请号：US15389544
申请日：2016-12-23
申请人： VIA TECHNOLOGIES, INC.
发明人： VANESSA CANAC , JAMES R. LUNDBERG
IPC分类号： G06F1/12 , G06F13/42
CPC分类号： G06F13/4243 , G06F1/12 , G06F13/4217 , G11C7/1072 , G11C8/18
摘要： An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.

103. 发明申请

US20170039156A1 COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE 审中-公开
标题翻译：具有串行通信接口和并行通信接口的通信控制系统
公开(公告)号：US20170039156A1
公开(公告)日：2017-02-09
申请号：US15289613
申请日：2016-10-10
申请人： Bedrock Automation Platforms Inc.
发明人： James G. Calvin , Albert Rooyakkers , Pirooz Parvarandeh
IPC分类号： G06F13/40 , G06F1/26 , G06F13/42
CPC分类号： G06F13/4282 , G06F1/26 , G06F3/002 , G06F13/00 , G06F13/14 , G06F13/4022 , G06F13/4208 , G06F13/4217 , G06F13/4221 , G06F2213/0004 , G06F2213/0022
摘要： A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.
摘要翻译：公开了一种通信控制系统，其包括用于将多个输入/输出模块与控制模块耦合的串行通信接口和并行通信接口。串行通信接口被配置为并行地将多个输入/输出模块连接到控制模块以在多个输入/输出模块和控制模块之间传送信息，并且并行通信接口被配置为分开地连接多个输入/输出模块到控制模块以在多个输入/输出模块和控制模块之间传送信息，并在多个输入/输出模块中的各个输入/输出模块之间传送信息。串行通信接口可以包括多点总线，并且并行通信接口可以包括交叉开关。

104. 发明申请

US20160085704A1 USB isochronous transfer over a non-USB network 审中-公开
标题翻译：通过非USB网络进行USB同步传输
公开(公告)号：US20160085704A1
公开(公告)日：2016-03-24
申请号：US14963373
申请日：2015-12-09
申请人： Valens Semiconductor Ltd.
发明人： Eyran Lida , Aviv Salamon
IPC分类号： G06F13/38 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4217 , H04L12/2832 , H04L12/2838 , H04L2012/2849 , H04N21/4305 , H04N21/43615 , H04N21/43632
摘要： Methods and systems for synchronizing USB 2.0 isochronous IN and OUT transfer clocks over a non-USB network. One method for synchronizing isochronous IN transfer clocks includes: receiving, by a USB host adaptor (USBH), packets from a USB host; writing in each packet an indication of the time in which the packet was received by the USBH; sending the packets from the USBH to a USB device adaptor (USBD) over the network; and synchronizing the USBD clock to the USBH clock based on a property related to the received packets.
摘要翻译：通过非USB网络同步USB 2.0同步IN和OUT传输时钟的方法和系统。用于同步等时IN传输时钟的一种方法包括：通过USB主机适配器（USBH）接收来自USB主机的分组; 在每个分组中写入由USBH接收分组的时间的指示; 通过网络将数据包从USBH发送到USB设备适配器（USBD）; 并根据与接收到的数据包相关的属性将USBD时钟同步到USBH时钟。

105. 发明授权

US09262362B2 Multi-cycle delay for communication buses 有权
标题翻译：通讯总线多循环延时
公开(公告)号：US09262362B2
公开(公告)日：2016-02-16
申请号：US14041818
申请日：2013-09-30
申请人： Apple Inc.
发明人： Shu-Yi Yu , Timothy R. Paaske
IPC分类号： G06F3/00 , G06F5/00 , G06F13/40 , G06F9/38
CPC分类号： G06F13/4068 , G06F9/3869 , G06F13/4217 , G06F2213/0038
摘要： A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.
摘要翻译：公开了可以补偿可能随总线的操作条件而变化的总线时序的系统。该系统可以包括通信总线，被配置为经由通信总线发送数据的第一功能单元和被配置为经由总线接收数据的第二功能单元。第一功能单元可以经由通信总线向第二功能单元发送第一值。第一功能单元还可以被配置为响应于从发送第一数据值开始经过第一时间段的确定来断言数据有效信号。第二功能单元可以被配置为接收第一数据值并且取决于数据有效信号对第一数据值进行采样。

106. 发明申请

US20150095535A1 MULTI-CYCLE DELAY FOR COMMUNICATION BUSES 有权
标题翻译：多通道延时通讯
公开(公告)号：US20150095535A1
公开(公告)日：2015-04-02
申请号：US14041818
申请日：2013-09-30
申请人： Apple Inc.
发明人： Shu-Yi Yu , Timothy R. Paaske
IPC分类号： G06F13/40
CPC分类号： G06F13/4068 , G06F9/3869 , G06F13/4217 , G06F2213/0038
摘要： A system is disclosed that may compensate for bus timing that may vary over operating conditions of a bus. The system may include a communication bus, a first functional unit configured to transmit data via the communication bus, and a second functional unit configured to receive data via the bus. The first functional unit may transmit a first value via the communication bus to the second functional unit. The first functional unit may be further configured to assert a data valid signal responsive to a determination that a first time period has elapsed since the transmission of the first data value. The second functional unit may be configured to receive the first data value and sample the first data value dependent upon the data valid signal.
摘要翻译：公开了可以补偿可能随总线的操作条件而变化的总线时序的系统。该系统可以包括通信总线，被配置为经由通信总线发送数据的第一功能单元和被配置为经由总线接收数据的第二功能单元。第一功能单元可以经由通信总线向第二功能单元发送第一值。第一功能单元还可以被配置为响应于从发送第一数据值开始经过第一时间段的确定来断言数据有效信号。第二功能单元可以被配置为接收第一数据值并且取决于数据有效信号对第一数据值进行采样。

107. 发明申请

US20140281759A1 BUS PROTOCOL CHECKER, SYSTEM ON CHIP INCLUDING THE SAME, BUS PROTOCOL CHECKING METHOD 有权
标题翻译：总线协议检查器，包括其的芯片系统，总线协议检查方法
公开(公告)号：US20140281759A1
公开(公告)日：2014-09-18
申请号：US14199088
申请日：2014-03-06
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： DEUM-JI WOO , YONG JE LEE , YOUNG-JUN KWON
IPC分类号： G06F13/42 , G06F11/07
CPC分类号： G06F11/0766 , G06F11/0745 , G06F13/4217 , G06F2213/0038
摘要： A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.
摘要翻译：片上系统（SoC）包括系统总线; 通过系统总线输出总线信号的多个知识产权（IP）; 以及一个或多个检查器，其被设置为对应于所述多个IP中的至少一些，其中所述检验器包括：用于设置关于将执行总线协议检查操作的检查对象和列表的信息的第一环境设置寄存器，其中该设置可以根据从外部经由系统总线的访问而变化; 以及接收总线信号的检查逻辑，并且根据在第一环境设置寄存器中设置的信息对总线信号中包括的信号执行总线协议检查操作。

108. 发明申请

US20130198301A1 System and Method for Conveying Information 有权
标题翻译：输送信息的系统和方法
公开(公告)号：US20130198301A1
公开(公告)日：2013-08-01
申请号：US13705087
申请日：2012-12-04
申请人： Steven C. Miller , Thomas Edward McGee , Bruce Alan Strangfeld
发明人： Steven C. Miller , Thomas Edward McGee , Bruce Alan Strangfeld
IPC分类号： G06F15/16
CPC分类号： H03M13/05 , G06F13/4217 , G06F15/16
摘要： A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, of a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.
摘要翻译：用于传送数据的系统和方法包括确定在计算机模块处是否已经接收到交易请求信用的能力，指示可以发送交易请求消息的至少一部分的交易请求信用。该系统和方法还包括确定事务请求消息将被发送的能力，是否可以发送交易请求消息的至少一部分，并且如果可以发送交易请求消息的至少一部分被发送。

109. 发明授权

US08108664B2 Fast and compact circuit for bus inversion 有权
标题翻译：快速紧凑的电路用于总线反相
公开(公告)号：US08108664B2
公开(公告)日：2012-01-31
申请号：US12367941
申请日：2009-02-09
申请人： Mayur Joshi
发明人： Mayur Joshi
IPC分类号： G06F9/305 , G06F11/00 , G06F1/32 , G06F13/20 , H03K19/23
CPC分类号： G06F13/4217 , G06F7/501 , Y02D10/14 , Y02D10/151
摘要： A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.
摘要翻译：一个总线系统，在负责总线反转决策的电路中具有快速紧凑的多数选民。多数选民在具有两个分支的模拟电路中实现。一个分支总结了在不反转的情况下发送比特的优点，另外一个总结了利用反演发送比特的优点。多数选民通过同时比较每个分支中的当前驱动器来计算略微多于一个门延迟的总线反转决定。

110. 发明授权

US08102730B2 Single-clock, strobeless signaling system 有权
标题翻译：单时钟，无频闪信号系统
公开(公告)号：US08102730B2
公开(公告)日：2012-01-24
申请号：US12706662
申请日：2010-02-16
申请人： Donald C. Stark
发明人： Donald C. Stark
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G06F13/4217 , G11C7/1072 , G11C7/22
摘要： A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.
摘要翻译：信令系统包括信令路径，耦合到信令路径的主设备，耦合到信令路径的从设备和时钟发生器。从设备包括定时电路，用于产生具有相对于由时钟发生器提供的时钟信号的相位偏移的内部时钟信号，相位偏移至少部分地由信号路径上的信号传播时间确定。

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