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    • 101. 发明申请
    • Cutting implement with cartridge
    • 切割工具带墨盒
    • US20070227012A1
    • 2007-10-04
    • US11728655
    • 2007-03-26
    • Richard ConstantineMichael PetersonJavier VerduraJonathan LeeCody Man For Ma
    • Richard ConstantineMichael PetersonJavier VerduraJonathan LeeCody Man For Ma
    • F41B13/02
    • B26B5/001
    • A utility knife has a receiving cavity which opens through the body. A cartridge comprising a magazine of blades is removably insertable into the receiving cavity. A carrier within the body is manually operable for receiving a blade from the cartridge and positioning the blade for extension through the opening to present a cutting edge. The cartridge may be released from the utility knife body by depressing a button and withdrawing the cartridge. The cartridge is releasably held in place within the knife body and releasable when the blade carrier is in its retracted position and the release button is depressed. When the thumb button moves the blade carrier into its extended position to expose the knife blade, the cartridge is rendered unreleaseable even if the release button is depressed. The release button, which will enable removal of the magazine when depressed and blade carrier is in its retracted position, also serves to release of the blade from the blade carrier to permit removal of a used blade from the knife body when the blade carrier is in its extended position.
    • 实用刀具有通过身体开口的接收腔。 包括刀片盒的盒可移除地插入到容纳腔中。 主体内的载体可手动操作,用于从盒中接收刀片,并将刀片定位以延伸通过开口以呈现切削刃。 通过按下按钮并取出墨盒,可以从实用刀体释放墨盒。 盒可释放地保持在刀体内的适当位置,并且当刀片托架处于其缩回位置并且释放按钮被压下时可释放。 当拇指按钮将刀片托架移动到伸出位置以露出刀片时,即使释放按钮被按下,墨盒也不会释放。 释放按钮,当压下和刀片托架处于其缩回位置时,能够移除刀库,还用于将刀片从刀片托架上释放,以便当刀片托架处于刀片托架时从刀体移除刀片 其延伸位置。
    • 102. 发明申请
    • Cable sense mode for intelligent power saving in absence of link pulse
    • 电缆检测模式,用于在没有链路脉冲的情况下实现智能省电
    • US20070104124A1
    • 2007-05-10
    • US11269414
    • 2005-11-08
    • Jonathan LeeGregory YoungbloodDavid (Wei) Wang
    • Jonathan LeeGregory YoungbloodDavid (Wei) Wang
    • G08C17/00
    • H04L12/10
    • Certain embodiments of a cable sense mode for intelligent power saving in the absence of a link pulse may include detecting an energy level of an Ethernet link. The Ethernet link may couple a network adapter chip to a network. The power supplied to the network adapter chip may be adjusted based on the detected energy level. Power may be supplied to the network adapter chip if the detected energy level of the Ethernet link is greater than or equal to a particular energy level. Power may be reduced to the network adapter chip if the detected energy level of the Ethernet link is less than a particular energy level. An output signal and/or an interrupt signal may be generated that indicates a change in the detected energy level of the Ethernet link. Power may be provided to the circuitry that generates the output signal and the interrupt signal.
    • 在没有链路脉冲的情况下用于智能省电的电缆感测模式的某些实施例可以包括检测以太网链路的能量级别。 以太网链路可能将网络适配器芯片耦合到网络。 可以基于检测到的能量水平来调整提供给网络适配器芯片的功率。 如果检测到的以太网链路的能量级别大于或等于特定能级,则可以向网络适配器芯片供电。 如果检测到的以太网链路的能量级别小于特定的能级,则电源可能会减少到网络适配器芯片。 可以生成指示以太网链路检测到的能级的变化的输出信号和/或中断信号。 可以向产生输出信号和中断信号的电路提供功率。
    • 104. 发明申请
    • Method and apparatus of detecting voltage for battery pack
    • 检测电池组电压的方法和装置
    • US20060290355A1
    • 2006-12-28
    • US11442873
    • 2006-05-30
    • Jonathan Lee
    • Jonathan Lee
    • G01N27/416
    • G01R31/3624
    • Disclosed is a method and apparatus of detecting voltage of a battery cell in consideration of impedance of conductive wires connecting a plurality of battery cells constituting the battery pack. The method of detecting voltage of at least one battery cell in a battery pack, in which the battery cell is connected through a conductive wire, includes the steps of storing impedance of the conductive wire from a part connected to a voltage detector to a part connected with the corresponding battery cell, detecting current of the battery pack, multiplying the impedance of the conductive wire corresponding to each battery cell and the current to calculate a correction value of each battery cell, detecting voltage of each battery cell, and correcting the voltage of each battery cell on the basis of the correction value of each battery cell. Further, the apparatus of detecting voltage of at least one battery cell in a battery pack, in which the battery cell is connected through a conductive wire, includes a voltage detector detecting the voltage of each battery cell, a memory storing impedance of the conductive wire from a part connected to a voltage detector to a part connected with the corresponding battery cell, a current detector detecting current of the battery pack, and a controller multiplying the impedance of the conductive wire corresponding to each battery cell and the current to calculate a correction value of each battery cell, and correcting the voltage of each battery cell on the basis of the correction value of each battery cell.
    • 考虑到连接构成电池组的多个电池单元的导线的阻抗,检测电池单元的电压的方法和装置。 检测电池组中至少一个电池单元的电压的方法,其中电池单元通过导线连接,包括以下步骤:将导线从与电压检测器连接的部分的阻抗存储到连接的部分 利用对应的电池单元,检测电池组的电流,乘以对应于每个电池单元的导线的阻抗和电流,以计算每个电池单元的校正值,检测每个电池单元的电压,以及校正每个电池单元的电压 每个电池单元基于每个电池单元的校正值。 此外,检测电池单元通过导线连接的电池组中的至少一个电池单元的电压的装置包括检测每个电池单元的电压的电压检测器,存储有导线的阻抗的存储器 从连接到电压检测器的部分到与相应电池单元连接的部分,电流检测器检测电池组的电流,以及控制器,将对应于每个电池单元的导线的阻抗与电流相乘以计算校正 并且基于每个电池单元的校正值来校正每个电池单元的电压。
    • 105. 发明申请
    • Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled
    • 安全高效的芯片掉电的方法和系统在器件未使能时最小化电流
    • US20060288245A1
    • 2006-12-21
    • US11269419
    • 2005-11-08
    • Jonathan Lee
    • Jonathan Lee
    • G06F1/32
    • G06F1/3296G06F1/3209Y02D10/172
    • Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.
    • 当设备未启用时,用于安全和有效地断电和绘制最小电流的方法和系统的某些实施例可包括在网络适配器芯片(NAC)内接收指示降低的功率模式的信号。 基于该信号,NAC可以控制向NAC内的电路提供降低的电压的片外电压源。 可以包括第一PNP晶体管和第二PNP晶体管的片外电压源可以将电压降低到第一电压和第二电压。 NAC还可以将通过片外电压源的电流减小到大约零安培,将片外电压源的输出电压减小到大约零伏特。 可以反馈第一电压和/或第二电压以控制片外电压源的输出电压和电流。
    • 109. 发明申请
    • Method and system for direct access memory testing of an integrated circuit
    • 用于集成电路直接存取存储器测试的方法和系统
    • US20050060621A1
    • 2005-03-17
    • US10940146
    • 2004-09-13
    • Jonathan LeeXiaogang ZhuAndrew Hwang
    • Jonathan LeeXiaogang ZhuAndrew Hwang
    • G11C29/48G11C29/00
    • G11C29/48G11C2029/0401
    • Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.
    • 可以在用于测试集成电路的方法和系统中找到本发明的方面,并且可以包括地址选择器,数据选择器和耦合到信号发生器的分级寄存器。 地址选择器可以包括直接访问存储器测试(DAMT)模式地址控制输入和耦合到被测嵌入式存储器件(DUT)的一个或多个输出地址引脚。 数据选择器可以耦合到信号发生器的至少一个数据引脚和控制引脚,并且可以包括DAMT模式数据控制输入和耦合到嵌入式存储器DUT的至少一个数据输出。 包括其输入时钟速率四分之一(¼)的第一输出时钟速率并与DUT突发写入频率匹配的分级寄存器可以耦合到数据选择器的输入端。 DAMT模式控制可以配置用于DAMT操作的存储器DUT。