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101. 发明授权

US07462930B2 Stack chip and stack chip package having the same 有权
标题翻译：堆栈芯片和堆栈芯片封装有相同的
公开(公告)号：US07462930B2
公开(公告)日：2008-12-09
申请号：US11627791
申请日：2007-01-26
申请人： Jong-Joo Lee , Dong-Ho Lee
发明人： Jong-Joo Lee , Dong-Ho Lee
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/66 , H01L24/48 , H01L24/73 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73257 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.
摘要翻译：提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。半导体芯片具有芯片焊盘，输入/输出缓冲器和通过电路布线连接的内部电路。半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。半导体芯片包括第一芯片和第二芯片。第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

102. 发明申请

US20080157394A1 Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages 有权
标题翻译：半导体封装，堆叠半导体封装以及制造半导体封装和堆叠半导体封装的方法
公开(公告)号：US20080157394A1
公开(公告)日：2008-07-03
申请号：US12003544
申请日：2007-12-28
申请人： Yong-Chai Kwon , Dong-Ho Lee
发明人： Yong-Chai Kwon , Dong-Ho Lee
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/3121 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05008 , H01L2224/05026 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/12044 , H01L2924/15311 , H01L2924/351 , H01L2924/00 , H01L2224/05099 , H01L2224/03
摘要： A semiconductor package may include a semiconductor pattern, a bonding pad, and a polymer insulation member. The semiconductor pattern may include a semiconductor device and first hole. The bonding pad may include a wiring pattern and plug. The wiring pattern may be formed on an upper face of the semiconductor pattern. The plug may extend from the wiring pattern to fill the first hole. The polymer insulation member may be formed on a lower face of the semiconductor pattern and may include a second hole exposing a lower end of the plug. A method of manufacturing a semiconductor package may include forming a first hole through a semiconductor substrate; forming a bonding pad and plug; attaching a supporting member to the upper face of the substrate; reducing a thickness of the substrate; forming a polymer insulation member on the lower face of the substrate; and cutting the substrate.
摘要翻译：半导体封装可以包括半导体图案，接合焊盘和聚合物绝缘构件。半导体图案可以包括半导体器件和第一孔。接合焊盘可以包括布线图案和插头。布线图案可以形成在半导体图案的上表面上。插头可以从布线图案延伸以填充第一孔。聚合物绝缘构件可以形成在半导体图案的下表面上，并且可以包括暴露插头的下端的第二孔。制造半导体封装的方法可以包括通过半导体衬底形成第一孔; 形成焊盘和插头; 将支撑构件附接到所述基板的上表面; 减小基板的厚度; 在所述基板的下表面上形成聚合物绝缘部件; 并切割基板。

103. 发明申请

US20070170556A1 Semiconductor device having flange structure 审中-公开
标题翻译：具有法兰结构的半导体器件
公开(公告)号：US20070170556A1
公开(公告)日：2007-07-26
申请号：US11635011
申请日：2006-12-07
申请人： Hyun-Soo Chung , Dong-Hyeon Jang , In-Young Lee , Dong-Ho Lee
发明人： Hyun-Soo Chung , Dong-Hyeon Jang , In-Young Lee , Dong-Ho Lee
IPC分类号： H01L23/495
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05548 , H01L2224/05557 , H01L2224/13 , H01L2224/13099 , H01L2924/00014 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H05K1/111 , H05K3/062 , H05K3/3452 , H05K3/3457 , H05K2201/09745 , H05K2203/1184 , Y02P70/611 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： A semiconductor device may include a semiconductor element. A layer of material may be provided on the semiconductor element which may have an opening through which a bond pad may be exposed. At least one flange structure may be provided on the first bond pad, the at least one flange structure made of at least two metal layers with different etch rates.
摘要翻译：半导体器件可以包括半导体元件。可以在半导体元件上提供一层材料，该层可以具有可以暴露接合焊盘的开口。可以在第一接合焊盘上提供至少一个凸缘结构，所述至少一个凸缘结构由具有不同蚀刻速率的至少两个金属层制成。

104. 发明申请

US20070153176A1 COLOR FILTER SUBSTRATE AND LIQUID CRYSTAL DISPLAY APPARATUS HAVING THE SAME 审中-公开
标题翻译：彩色滤光片和液晶显示装置
公开(公告)号：US20070153176A1
公开(公告)日：2007-07-05
申请号：US11686138
申请日：2007-03-14
申请人： Yong-Ho Yang , Dong-Ho Lee
发明人： Yong-Ho Yang , Dong-Ho Lee
IPC分类号： G02F1/1335
CPC分类号： G02F1/133514 , G02F1/133555 , G02F2001/133357
摘要： A reflection-transmission LCD includes substrates arranged opposite to each other, a color filter layer formed on at least one of the substrates, a hole formed in that color filter layer to substantially minimize differences in color reproducibility between reflective mode operation and transmission mode operation, a planarization layer formed on a first of the substrates and including a first insulating layer formed on the color filter layer that covers the at least one hole and a second insulating layer formed on the first insulating layer for substantially planarizing step differences due to the hole formed in the at least one color filter layer a common electrode formed on the second insulating layer, liquid crystal material arranged between the first substrate and the second substrate, a gate insulating layer formed on the second substrate, and a third insulating layer formed on the gate insulating layer.
摘要翻译：反射透射LCD包括彼此相对布置的基板，形成在至少一个基板上的滤色器层，形成在该滤色器层中的孔，以基本上最小化反射模式操作和透射模式操作之间的颜色再现性的差异，平坦化层，形成在第一基板上，并且包括形成在覆盖所述至少一个孔的滤色器层上的第一绝缘层和形成在第一绝缘层上的第二绝缘层，用于基本上平坦化由于形成的孔形成的台阶差在所述至少一个滤色器层中，形成在所述第二绝缘层上的公共电极，布置在所述第一基板和所述第二基板之间的液晶材料，形成在所述第二基板上的栅极绝缘层，以及形成在所述栅极上的第三绝缘层绝缘层。

105. 发明授权

US07206042B2 Color filter substrate and liquid crystal display apparatus having the same 有权
标题翻译：滤色器基板和具有该滤色器基板的液晶显示装置
公开(公告)号：US07206042B2
公开(公告)日：2007-04-17
申请号：US10795515
申请日：2004-03-09
申请人： Yong-Ho Yang , Dong-Ho Lee
发明人： Yong-Ho Yang , Dong-Ho Lee
IPC分类号： G02F1/1335 , G09G3/35
CPC分类号： G02F1/133514 , G02F1/133555 , G02F2001/133357
摘要： The LCD apparatus having a color filter substrate including a first area and a second area adjacent to the first area. The color filter substrate includes a plurality of color pixels having different colors with respect to each other. The color pixels have an element formed thereon to partially expose the substrate. A transmission electrode is formed on the color filter and on the substrate exposed through the element. At least two color pixels of the color pixels have different sizes from each other. Thus, the LCD apparatus has improved display properties.
摘要翻译：所述LCD装置具有滤色器基板，所述滤色器基板包括与所述第一区域相邻的第一区域和第二区域。滤色器基板包括彼此不同颜色的多个彩色像素。彩色像素具有形成在其上以部分地暴露衬底的元件。传输电极形成在滤色器上和通过元件曝光的基板上。彩色像素的至少两个彩色像素具有彼此不同的尺寸。因此，LCD装置具有改进的显示特性。

106. 发明申请

US20070081321A1 Backlight unit and display apparatus having the same 审中-公开
标题翻译：背光单元及其显示装置
公开(公告)号：US20070081321A1
公开(公告)日：2007-04-12
申请号：US11247882
申请日：2005-10-10
申请人： Seung-Ho Ahn , Do-Hyung Kim , Dong-Ho Lee
发明人： Seung-Ho Ahn , Do-Hyung Kim , Dong-Ho Lee
IPC分类号： G09F13/04
CPC分类号： G02F1/133615 , G02B6/0055 , G02B6/0068 , G02F1/133603 , G02F1/133604 , G02F1/133609
摘要： In a backlight unit and a display apparatus having the backlight unit, the backlight unit includes a first light source, a second light source, and an optical plate having a lower surface facing the second light source and an upper surface substantially parallel with the lower surface. The first light source generating a first light having a first wavelength range. The second light source generating a second light having a second wavelength range different from the first wavelength range to compensate the first light. Thus, display quality of display apparatus may be improved.
摘要翻译：在具有背光单元的背光单元和显示装置中，背光单元包括第一光源，第二光源和具有面向第二光源的下表面的光学板和与下表面大致平行的上表面。第一光源产生具有第一波长范围的第一光。第二光源产生具有与第一波长范围不同的第二波长范围的第二光，以补偿第一光。因此，可以提高显示装置的显示质量。

107. 发明授权

US07196000B2 Method for manufacturing a wafer level chip scale package 有权
标题翻译：制造晶圆级芯片级封装的方法
公开(公告)号：US07196000B2
公开(公告)日：2007-03-27
申请号：US10690782
申请日：2003-10-21
申请人： Jin-Hyuk Lee , Gu-Sung Kim , Dong-Ho Lee , Dong-Hyeon Jang
发明人： Jin-Hyuk Lee , Gu-Sung Kim , Dong-Ho Lee , Dong-Hyeon Jang
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/02 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05548 , H01L2224/13099 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433
摘要： A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.
摘要翻译：提供了具有芯片焊盘和钝化层的半导体芯片的半导体晶片。第一和第二电介质层依次形成在钝化层上。第一和第二电介质层形成包括压花部分，即具有非平面表面的球垫区域。在所得到的包括压纹部分的结构上形成金属布线层。第三电介质层形成在金属布线层上。位于压花部分上的第三电介质层的一部分被去除以形成球垫。在浮雕球垫上形成焊球。利用压纹球垫，焊球和金属布线层之间的接触面积增加，从而提高连接可靠性。

108. 发明申请

US20070040280A1 Multi-chip package for reducing parasitic load of pin 有权
标题翻译：用于减少引脚寄生负载的多芯片封装
公开(公告)号：US20070040280A1
公开(公告)日：2007-02-22
申请号：US11589192
申请日：2006-10-30
申请人： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
发明人： Byung-Se So , Dong-Ho Lee , Hyun-Soon Jang
IPC分类号： H01L23/52
CPC分类号： H01L24/49 , G11C5/00 , G11C5/06 , H01L23/50 , H01L24/48 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01006 , H01L2924/01055 , H01L2924/01075 , H01L2924/30105 , H01L2224/45099 , H01L2224/05599
摘要： Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed. Also, when a signal that is not necessarily transmitted at high speed is applied to a pin, semiconductor chips can be packaged according to the preexisting methods.
摘要翻译：多芯片封装包括第一至第N个半导体芯片，每个半导体芯片包括输入/输出焊盘，耦合到输入/输出焊盘的输入/输出驱动器和内部电路。第一至第N半导体芯片中的每一个包括用于耦合内部输入/输出驱动器和内部电路的内部焊盘。第一至第N半导体芯片的内部焊盘彼此耦合，例如经由安装在基板上的公共焊盘。第一半导体芯片的输入/输出焊盘直接接收通过多芯片封装的相应引脚传输的输入/输出信号。第二至第N半导体芯片通过彼此耦合的内部焊盘间接接收输入/输出信号。当信号以高速传输到引脚时，多芯片封装可以通过将引脚的寄生负载保持在至少单个芯片的电平来提高信号兼容性。此外，当不需要高速传输的信号被施加到引脚时，可以根据预先存在的方法来封装半导体芯片。

109. 发明申请

US20060221268A1 Display device 失效
公开(公告)号：US20060221268A1
公开(公告)日：2006-10-05
申请号：US11138211
申请日：2005-05-27
申请人： Hyung-Seok Ko , Soo-Jin Kim , Dong-Ho Lee
发明人： Hyung-Seok Ko , Soo-Jin Kim , Dong-Ho Lee
IPC分类号： G02F1/1333
CPC分类号： G02F1/133308 , G02B6/0018 , G02B6/002 , G02B6/0088 , G02F2001/133322 , G02F2001/133342
摘要： A display device including a display panel displaying an image; a light source unit supplying light to the display panel, and a light guiding unit including a light guiding section which has a light receiving surface positioned adjacent to the light source unit and a light emitting surface positioned opposite to the display panel and which guides light emitted from the light source unit to the display panel, a side wall section forming a reception space for receiving the display panel along the edges of the light guiding section, and a fixing section fixing the light guiding section to the display device.

110. 发明申请

US20060194366A1 MULTI-CHIP BALL GRID ARRAY PACKAGE 审中-公开
标题翻译：多芯球网阵列包
公开(公告)号：US20060194366A1
公开(公告)日：2006-08-31
申请号：US11382245
申请日：2006-05-08
申请人： Jong-Joo Lee , Dong-Ho Lee
发明人： Jong-Joo Lee , Dong-Ho Lee
IPC分类号： H01L21/00
CPC分类号： H01L23/66 , H01L23/3128 , H01L23/50 , H01L23/525 , H01L23/5286 , H01L24/10 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2223/6627 , H01L2224/05001 , H01L2224/05026 , H01L2224/05124 , H01L2224/05548 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2225/0651 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2924/00014 , H01L2924/01078 , H01L2924/12042 , H01L2924/15311 , H01L2924/1903 , H01L2924/19033 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , Y10S257/924 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an increase in thickness of the package. Further, each pair of rerouting lines on upper and lower rerouted chips includes two or more interconnection bumps. This reduces inductance and resistance of electric signal propagation. Therefore, the multi-chip BGA package of this invention can realize small, thin, high-speed and high-density memory devices.
摘要翻译：多芯片BGA封装具有两个或更多个重新路由的芯片，每个芯片具有一个或多个电极板。电极板在重新布线的芯片上与重新路由线共面，并且可以用作去耦电容器，从而降低电源电压波动中的同时开关噪声，而不会增加封装的厚度。此外，上，下重路由芯片上的每对重新路由线包括两个或多个互连凸块。这降低了电信号传播的电感和电阻。因此，本发明的多芯片BGA封装可以实现小型，薄型，高速和高密度的存储器件。

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